mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 14:14:32 +00:00
fbe127f7b5
Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
137 lines
2.6 KiB
Text
137 lines
2.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
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// Based on sun50i-a64-pine64.dts, which is:
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// Copyright (c) 2016 ARM Ltd.
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#include "sun50i-a64.dtsi"
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#include "sun50i-a64-cpu-opp.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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&codec_analog {
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cpvdd-supply = <®_eldo1>;
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};
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&cpu0 {
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cpu-supply = <®_dcdc2>;
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};
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&cpu1 {
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cpu-supply = <®_dcdc2>;
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};
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&cpu2 {
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cpu-supply = <®_dcdc2>;
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};
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&cpu3 {
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cpu-supply = <®_dcdc2>;
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};
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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vmmc-supply = <®_dcdc1>;
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disable-wp;
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bus-width = <4>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
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status = "okay";
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};
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&r_rsb {
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status = "okay";
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axp803: pmic@3a3 {
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compatible = "x-powers,axp803";
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reg = <0x3a3>;
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interrupt-parent = <&r_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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};
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};
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#include "axp803.dtsi"
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®_aldo2 {
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-pl";
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};
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®_aldo3 {
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regulator-always-on;
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-name = "vcc-pll-avcc";
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};
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®_dcdc1 {
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regulator-always-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc-3v3";
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};
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®_dcdc2 {
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regulator-always-on;
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regulator-min-microvolt = <1040000>;
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regulator-max-microvolt = <1300000>;
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regulator-name = "vdd-cpux";
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};
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/* DCDC3 is polyphased with DCDC2 */
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®_dcdc5 {
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-name = "vcc-dram";
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};
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®_dcdc6 {
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-sys";
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};
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®_eldo1 {
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vdd-1v8-lpddr";
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};
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®_fldo1 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-name = "vcc-1v2-hsic";
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};
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/*
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* The A64 chip cannot work without this regulator off, although
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* it seems to be only driving the AR100 core.
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* Maybe we don't still know well about CPUs domain.
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*/
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®_fldo2 {
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-name = "vdd-cpus";
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};
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®_rtc_ldo {
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regulator-name = "vcc-rtc";
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};
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