Lokesh Vutla ccdb7c2255 armv7r: K3: Allow SPL to run only on core 0 ... Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>		2018-11-26 22:52:11 -05:00
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include/mach	ram: Introduce K3 AM654 DDR Sub System driver	2018-11-16 16:51:58 -05:00
am6_init.c	armv7R: K3: am654: Add support for triggering ddr init from SPL	2018-11-16 16:51:59 -05:00
arm64-mmu.c	armv8: K3: am654: Add custom MMU support	2018-09-11 08:32:55 -04:00
common.c	armv7R: K3: am654: Add support to start ATF from R5 SPL	2018-11-16 16:51:58 -05:00
common.h	armv7R: K3: am654: Enable MPU regions	2018-11-16 16:51:58 -05:00
config.mk	armv7R: K3: am654: Add support for generating build targets	2018-11-16 16:51:58 -05:00
Kconfig	armv7R: K3: am654: Add support to start ATF from R5 SPL	2018-11-16 16:51:58 -05:00
lowlevel_init.S	armv7r: K3: Allow SPL to run only on core 0	2018-11-26 22:52:11 -05:00
Makefile	armv7r: K3: Allow SPL to run only on core 0	2018-11-26 22:52:11 -05:00
r5_mpu.c	armv7R: K3: am654: Enable MPU regions	2018-11-16 16:51:58 -05:00