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u-boot/board/freescale/ls1043aqds
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York Sun 4961eafc25 armv8: layerscape: Update early MMU for DDR after initialization 
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
..
ddr.c armv8: layerscape: Rewrite memory reservation 2017-03-14 08:44:03 -07:00
ddr.h board/freescale: Update ddr clk_adjust 2016-06-03 14:06:57 -07:00
eth.c armv8: ls1043aqds: make sure fixed-link property is big endian 2016-04-06 08:34:55 -07:00
Kconfig NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST 2017-01-24 10:33:59 -05:00
ls1043aqds.c armv8: layerscape: Update early MMU for DDR after initialization 2017-03-14 08:44:03 -07:00
ls1043aqds_pbi.cfg armv8/ls1043aqds: add LS1043AQDS board support 2015-11-30 09:11:10 -08:00
ls1043aqds_qixis.h armv8/ls1043aqds: add LS1043AQDS board support 2015-11-30 09:11:10 -08:00
ls1043aqds_rcw_nand.cfg armv8/ls1043aqds/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
ls1043aqds_rcw_sd_ifc.cfg armv8/ls1043aqds/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
ls1043aqds_rcw_sd_qspi.cfg armv8/ls1043aqds: add QSPI support in SD boot 2016-01-27 08:28:55 -08:00
MAINTAINERS armv8: ls1043aqds: Update MAINTAINERS 2016-07-26 09:01:58 -07:00
Makefile armv8/ls1043aqds: add LS1043AQDS board support 2015-11-30 09:11:10 -08:00
README armv8: fsl-layerscape: Organize SoC overview at common location 2016-06-03 14:12:50 -07:00

README 

Overview
--------
The LS1043A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1043A
LayerScape Architecture processor. The LS1043AQDS provides SW development
platform for the Freescale LS1043A processor series, with a complete
debugging environment.

LS1043A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.

 LS1043AQDS board Overview
 -----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express - 3.0
      - SGMII, SGMII 2.5
      - QSGMII
      - SATA 3.0
      - XFI
 - DDR Controller
     - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
 -IFC/Local Bus
    - One in-socket 128 MB NOR flash 16-bit data bus
    - One 512 MB NAND flash with ECC support
    - PromJet Port
    - FPGA connection
 - USB 3.0
    - Three high speed USB 3.0 ports
    - First USB 3.0 port configured as Host with Type-A connector
    - The other two USB 3.0 ports configured as OTG with micro-AB connector
 - SDHC port connects directly to an adapter card slot, featuring:
    - Optional clock feedback paths, and optional high-speed voltage translation assistance
    - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
    - eMMC memory devices
 - DSPI: Onboard support for three SPI flash memory devices
 - 4 I2C controllers
 - One SATA onboard connectors
 - UART
   - Two 4-pin serial ports at up to 115.2 Kbit/s
   - Two DB9 D-Type connectors supporting one Serial port each
 - ARM JTAG support

Memory map from core's view
----------------------------
Start Address	End Address	Description		Size
0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB

Booting Options
---------------
a) Promjet Boot
b) NOR boot
c) NAND boot
d) SD boot
e) QSPI boot