mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
54841ab50c
The hush shell dynamically allocates (and re-allocates) memory for the
argument strings in the "char *argv[]" argument vector passed to
commands. Any code that modifies these pointers will cause serious
corruption of the malloc data structures and crash U-Boot, so make
sure the compiler can check that no such modifications are being done
by changing the code into "char * const argv[]".
This modification is the result of debugging a strange crash caused
after adding a new command, which used the following argument
processing code which has been working perfectly fine in all Unix
systems since version 6 - but not so in U-Boot:
int main (int argc, char **argv)
{
while (--argc > 0 && **++argv == '-') {
/* ====> */ while (*++*argv) {
switch (**argv) {
case 'd':
debug++;
break;
...
default:
usage ();
}
}
}
...
}
The line marked "====>" will corrupt the malloc data structures and
usually cause U-Boot to crash when the next command gets executed by
the shell. With the modification, the compiler will prevent this with
an
error: increment of read-only location '*argv'
N.B.: The code above can be trivially rewritten like this:
while (--argc > 0 && **++argv == '-') {
char *arg = *argv;
while (*++arg) {
switch (*arg) {
...
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
750 lines
19 KiB
C
750 lines
19 KiB
C
/**
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* @file powerspan.c Source file for PowerSpan II code.
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*/
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/*
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* (C) Copyright 2005
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* AMIRIX Systems Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include "powerspan.h"
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#define tolower(x) x
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#include "ap1000.h"
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#ifdef INCLUDE_PCI
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/** Write one byte with byte swapping.
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* @param addr [IN] the address to write to
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* @param val [IN] the value to write
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*/
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void write1 (unsigned long addr, unsigned char val)
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{
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volatile unsigned char *p = (volatile unsigned char *) addr;
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("write1: addr=%08x val=%02x\n", addr, val);
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}
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#endif
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*p = val;
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PSII_SYNC ();
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}
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/** Read one byte with byte swapping.
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* @param addr [IN] the address to read from
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* @return the value at addr
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*/
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unsigned char read1 (unsigned long addr)
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{
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unsigned char val;
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volatile unsigned char *p = (volatile unsigned char *) addr;
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val = *p;
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PSII_SYNC ();
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("read1: addr=%08x val=%02x\n", addr, val);
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}
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#endif
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return val;
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}
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/** Write one 2-byte word with byte swapping.
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* @param addr [IN] the address to write to
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* @param val [IN] the value to write
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*/
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void write2 (unsigned long addr, unsigned short val)
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{
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volatile unsigned short *p = (volatile unsigned short *) addr;
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
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((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
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}
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#endif
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*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
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PSII_SYNC ();
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}
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/** Read one 2-byte word with byte swapping.
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* @param addr [IN] the address to read from
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* @return the value at addr
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*/
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unsigned short read2 (unsigned long addr)
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{
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unsigned short val;
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volatile unsigned short *p = (volatile unsigned short *) addr;
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val = *p;
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val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
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PSII_SYNC ();
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
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val);
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}
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#endif
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return val;
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}
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/** Write one 4-byte word with byte swapping.
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* @param addr [IN] the address to write to
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* @param val [IN] the value to write
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*/
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void write4 (unsigned long addr, unsigned long val)
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{
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volatile unsigned long *p = (volatile unsigned long *) addr;
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
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((val & 0xFF000000) >> 24) |
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((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) |
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((val & 0x0000FF00) << 8));
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}
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#endif
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*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
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PSII_SYNC ();
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}
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/** Read one 4-byte word with byte swapping.
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* @param addr [IN] the address to read from
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* @return the value at addr
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*/
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unsigned long read4 (unsigned long addr)
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{
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unsigned long val;
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volatile unsigned long *p = (volatile unsigned long *) addr;
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val = *p;
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val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
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((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
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PSII_SYNC ();
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
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val);
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}
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#endif
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return val;
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}
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int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
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unsigned long *val)
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{
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unsigned int conAdrVal;
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unsigned int conDataReg = REG_CONFIG_DATA;
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unsigned int status;
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int ret_val = 0;
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/* DEST bit hardcoded to 1: local pci is PCI-2 */
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/* TYPE bit is hardcoded to 1: all config cycles are local */
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conAdrVal = (1 << 24)
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| ((bus & 0xFF) << 16)
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| ((dev & 0xFF) << 11)
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| ((fn & 0x07) << 8)
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| (reg & 0xFC);
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/* clear any pending master aborts */
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write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
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/* Load the conAdrVal value first, then read from pb_conf_data */
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write4 (REG_CONFIG_ADDRESS, conAdrVal);
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PSII_SYNC ();
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/* Note: documentation does not match the pspan library code */
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/* Note: *pData comes back as -1 if device is not present */
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switch (width) {
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case 4:
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*(unsigned int *) val = read4 (conDataReg);
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break;
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case 2:
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*(unsigned short *) val = read2 (conDataReg);
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break;
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case 1:
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*(unsigned char *) val = read1 (conDataReg);
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break;
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default:
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ret_val = ILLEGAL_REG_OFFSET;
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break;
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}
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PSII_SYNC ();
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/* clear any pending master aborts */
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status = read4 (REG_P1_CSR);
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if (status & CLEAR_MASTER_ABORT) {
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ret_val = NO_DEVICE_FOUND;
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write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
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}
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return ret_val;
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}
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int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
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unsigned long val)
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{
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unsigned int conAdrVal;
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unsigned int conDataReg = REG_CONFIG_DATA;
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unsigned int status;
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int ret_val = 0;
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/* DEST bit hardcoded to 1: local pci is PCI-2 */
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/* TYPE bit is hardcoded to 1: all config cycles are local */
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conAdrVal = (1 << 24)
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| ((bus & 0xFF) << 16)
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| ((dev & 0xFF) << 11)
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| ((fn & 0x07) << 8)
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| (reg & 0xFC);
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/* clear any pending master aborts */
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write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
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/* Load the conAdrVal value first, then read from pb_conf_data */
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write4 (REG_CONFIG_ADDRESS, conAdrVal);
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PSII_SYNC ();
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/* Note: documentation does not match the pspan library code */
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/* Note: *pData comes back as -1 if device is not present */
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switch (width) {
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case 4:
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write4 (conDataReg, val);
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break;
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case 2:
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write2 (conDataReg, val);
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break;
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case 1:
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write1 (conDataReg, val);
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break;
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default:
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ret_val = ILLEGAL_REG_OFFSET;
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break;
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}
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PSII_SYNC ();
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/* clear any pending master aborts */
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status = read4 (REG_P1_CSR);
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if (status & CLEAR_MASTER_ABORT) {
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ret_val = NO_DEVICE_FOUND;
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write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
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}
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return ret_val;
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}
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int pci_read_config_byte (int bus, int dev, int fn, int reg,
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unsigned char *val)
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{
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unsigned long read_val;
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int ret_val;
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ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
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*val = read_val & 0xFF;
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return ret_val;
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}
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int pci_write_config_byte (int bus, int dev, int fn, int reg,
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unsigned char val)
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{
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return PCIWriteConfig (bus, dev, fn, reg, 1, val);
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}
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int pci_read_config_word (int bus, int dev, int fn, int reg,
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unsigned short *val)
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{
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unsigned long read_val;
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int ret_val;
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ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
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*val = read_val & 0xFFFF;
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return ret_val;
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}
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int pci_write_config_word (int bus, int dev, int fn, int reg,
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unsigned short val)
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{
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return PCIWriteConfig (bus, dev, fn, reg, 2, val);
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}
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int pci_read_config_dword (int bus, int dev, int fn, int reg,
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unsigned long *val)
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{
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return PCIReadConfig (bus, dev, fn, reg, 4, val);
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}
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int pci_write_config_dword (int bus, int dev, int fn, int reg,
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unsigned long val)
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{
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return PCIWriteConfig (bus, dev, fn, reg, 4, val);
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}
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#endif /* INCLUDE_PCI */
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int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
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unsigned char theChipSel, unsigned char *theValue, int RWFlag)
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{
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int ret_val = 0;
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unsigned int reg_value;
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reg_value = PowerSpanRead (REG_I2C_CSR);
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if (reg_value & I2C_CSR_ACT) {
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printf ("Error: I2C busy\n");
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ret_val = I2C_BUSY;
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} else {
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reg_value = ((theI2CAddress & 0xFF) << 24)
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| ((theDevCode & 0x0F) << 12)
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| ((theChipSel & 0x07) << 9)
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| I2C_CSR_ERR;
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if (RWFlag == I2C_WRITE) {
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reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
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}
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PowerSpanWrite (REG_I2C_CSR, reg_value);
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udelay (1);
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do {
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reg_value = PowerSpanRead (REG_I2C_CSR);
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if ((reg_value & I2C_CSR_ACT) == 0) {
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if (reg_value & I2C_CSR_ERR) {
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ret_val = I2C_ERR;
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} else {
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*theValue =
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(reg_value & I2C_CSR_DATA) >>
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16;
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}
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}
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} while (reg_value & I2C_CSR_ACT);
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}
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return ret_val;
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}
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int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
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{
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return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
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theValue, I2C_READ);
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}
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int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
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{
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return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
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&theValue, I2C_WRITE);
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}
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int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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char cmd;
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int ret_val = 0;
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unsigned int address = 0;
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unsigned char value = 1;
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unsigned char read_value;
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int ii;
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int error = 0;
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unsigned char *mem_ptr;
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unsigned char default_eeprom[] = EEPROM_DEFAULT;
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if (argc < 2) {
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goto usage;
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}
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cmd = argv[1][0];
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if (argc > 2) {
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address = simple_strtoul (argv[2], NULL, 16);
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if (argc > 3) {
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value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
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}
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}
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switch (cmd) {
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case 'r':
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if (address > 256) {
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printf ("Illegal Address\n");
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goto usage;
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}
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printf ("@0x%x: ", address);
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for (ii = 0; ii < value; ii++) {
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if (EEPROMRead (address + ii, &read_value) !=
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0) {
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printf ("Read Error\n");
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} else {
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printf ("0x%02x ", read_value);
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}
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if (((ii + 1) % 16) == 0) {
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printf ("\n");
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}
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}
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printf ("\n");
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break;
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case 'w':
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if (address > 256) {
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printf ("Illegal Address\n");
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goto usage;
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}
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if (argc < 4) {
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goto usage;
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}
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if (EEPROMWrite (address, value) != 0) {
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printf ("Write Error\n");
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}
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break;
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case 'g':
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if (argc != 3) {
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goto usage;
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}
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mem_ptr = (unsigned char *) address;
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for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
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ii++) {
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if (EEPROMRead (ii, &read_value) != 0) {
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printf ("Read Error\n");
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error = 1;
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} else {
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*mem_ptr = read_value;
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mem_ptr++;
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}
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}
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break;
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case 'p':
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if (argc != 3) {
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goto usage;
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}
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mem_ptr = (unsigned char *) address;
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for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
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ii++) {
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if (EEPROMWrite (ii, *mem_ptr) != 0) {
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printf ("Write Error\n");
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error = 1;
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}
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mem_ptr++;
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}
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break;
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case 'd':
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if (argc != 2) {
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goto usage;
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}
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for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
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ii++) {
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if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
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printf ("Write Error\n");
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error = 1;
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}
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}
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break;
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default:
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goto usage;
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}
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goto done;
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usage:
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printf ("Usage:\n%s\n", cmdtp->help);
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done:
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return ret_val;
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}
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U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
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"read/write/copy to/from the PowerSpan II eeprom",
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"eeprom r OFF [NUM]\n"
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" - read NUM words starting at OFF\n"
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"eeprom w OFF VAL\n"
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" - write word VAL at offset OFF\n"
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"eeprom g ADD\n"
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" - store contents of eeprom at address ADD\n"
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"eeprom p ADD\n"
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" - put data stored at address ADD into the eeprom\n"
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"eeprom d\n" " - return eeprom to default contents");
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unsigned int PowerSpanRead (unsigned int theOffset)
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{
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volatile unsigned int *ptr =
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(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
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unsigned int ret_val;
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("PowerSpanRead: offset=%08x ", theOffset);
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}
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#endif
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ret_val = *ptr;
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PSII_SYNC ();
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#ifdef VERBOSITY
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if (gVerbosityLevel > 1) {
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printf ("value=%08x\n", ret_val);
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}
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#endif
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return ret_val;
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}
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void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
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{
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volatile unsigned int *ptr =
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(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
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|
#ifdef VERBOSITY
|
|
if (gVerbosityLevel > 1) {
|
|
printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
|
|
theValue);
|
|
}
|
|
#endif
|
|
*ptr = theValue;
|
|
PSII_SYNC ();
|
|
}
|
|
|
|
/**
|
|
* Sets the indicated bits in the indicated register.
|
|
* @param theOffset [IN] the register to access.
|
|
* @param theMask [IN] bits set in theMask will be set in the register.
|
|
*/
|
|
void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
|
|
{
|
|
volatile unsigned int *ptr =
|
|
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
|
|
unsigned int register_value;
|
|
|
|
#ifdef VERBOSITY
|
|
if (gVerbosityLevel > 1) {
|
|
printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
|
|
theOffset, theMask);
|
|
}
|
|
#endif
|
|
register_value = *ptr;
|
|
PSII_SYNC ();
|
|
|
|
register_value |= theMask;
|
|
*ptr = register_value;
|
|
PSII_SYNC ();
|
|
}
|
|
|
|
/**
|
|
* Clears the indicated bits in the indicated register.
|
|
* @param theOffset [IN] the register to access.
|
|
* @param theMask [IN] bits set in theMask will be cleared in the register.
|
|
*/
|
|
void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
|
|
{
|
|
volatile unsigned int *ptr =
|
|
(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
|
|
unsigned int register_value;
|
|
|
|
#ifdef VERBOSITY
|
|
if (gVerbosityLevel > 1) {
|
|
printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
|
|
theOffset, theMask);
|
|
}
|
|
#endif
|
|
register_value = *ptr;
|
|
PSII_SYNC ();
|
|
|
|
register_value &= ~theMask;
|
|
*ptr = register_value;
|
|
PSII_SYNC ();
|
|
}
|
|
|
|
/**
|
|
* Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
|
|
* Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they
|
|
* are outgoing from the standpoint of the local bus.
|
|
* @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7).
|
|
* @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
|
|
* @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
|
|
* @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
|
|
* @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
|
|
* @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
|
|
*/
|
|
int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
|
|
int theMemIOFlag, int theEndianness,
|
|
unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
|
|
{
|
|
unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
|
|
unsigned int reg_value = 0;
|
|
|
|
/* Make sure that the Slave Image is disabled */
|
|
PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
|
|
PB_SLAVE_CSR_IMG_EN);
|
|
|
|
/* Setup the mask required for requested PB Slave Image configuration */
|
|
reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
|
|
if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
|
|
reg_value |= PB_SLAVE_CSR_MEM_IO;
|
|
}
|
|
|
|
/* hardcoding the following:
|
|
TA_EN = 1
|
|
MD_EN = 0
|
|
MODE = 0
|
|
PRKEEP = 0
|
|
RD_AMT = 0
|
|
*/
|
|
PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
|
|
|
|
/* these values are not checked by software */
|
|
PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
|
|
PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
|
|
|
|
/* Enable the Slave Image */
|
|
PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
|
|
PB_SLAVE_CSR_IMG_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Configures a target image on the local bus, based on the parameters and some hardcoded system values.
|
|
* Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they
|
|
* are incoming from the standpoint of the local bus.
|
|
* In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
|
|
* base address will not be updated; makes sense given that the hosts own memory should be mapped to
|
|
* PCI address 0x00000000.
|
|
* @param theImageIndex [IN] the PowerSpan II image to set.
|
|
* @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
|
|
* @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
|
|
* @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
|
|
* @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
|
|
* @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
|
|
*/
|
|
int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
|
|
int theMemIOFlag, int theEndianness,
|
|
unsigned int theLocalBaseAddr,
|
|
unsigned int thePCIBaseAddr)
|
|
{
|
|
unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
|
|
unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
|
|
unsigned int reg_value = 0;
|
|
|
|
/* Make sure that the Slave Image is disabled */
|
|
PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
|
|
PB_SLAVE_CSR_IMG_EN);
|
|
|
|
/* Setup the mask required for requested PB Slave Image configuration */
|
|
reg_value =
|
|
PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
|
|
PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
|
|
if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
|
|
reg_value |= PX_TGT_MEM_IO;
|
|
}
|
|
|
|
/* hardcoding the following:
|
|
TA_EN = 1
|
|
BAR_EN = 1
|
|
MD_EN = 0
|
|
MODE = 0
|
|
DEST = 0
|
|
RTT = 01010
|
|
GBL = 0
|
|
CI = 0
|
|
WTT = 00010
|
|
PRKEEP = 0
|
|
MRA = 0
|
|
RD_AMT = 0
|
|
*/
|
|
PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
|
|
|
|
PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
|
|
theLocalBaseAddr);
|
|
|
|
if (thePCIBaseAddr != (unsigned int) NULL) {
|
|
PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
|
|
thePCIBaseAddr);
|
|
}
|
|
|
|
/* Enable the Slave Image */
|
|
PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
|
|
PB_SLAVE_CSR_IMG_EN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
char cmd;
|
|
int ret_val = 1;
|
|
unsigned int image_index;
|
|
unsigned int block_size;
|
|
unsigned int mem_io;
|
|
unsigned int local_addr;
|
|
unsigned int pci_addr;
|
|
int endianness;
|
|
|
|
if (argc != 8) {
|
|
goto usage;
|
|
}
|
|
|
|
cmd = argv[1][0];
|
|
image_index = simple_strtoul (argv[2], NULL, 16);
|
|
block_size = simple_strtoul (argv[3], NULL, 16);
|
|
mem_io = simple_strtoul (argv[4], NULL, 16);
|
|
endianness = argv[5][0];
|
|
local_addr = simple_strtoul (argv[6], NULL, 16);
|
|
pci_addr = simple_strtoul (argv[7], NULL, 16);
|
|
|
|
|
|
switch (cmd) {
|
|
case 'i':
|
|
if (tolower (endianness) == 'b') {
|
|
endianness = PX_TGT_CSR_BIG_END;
|
|
} else if (tolower (endianness) == 'l') {
|
|
endianness = PX_TGT_CSR_TRUE_LEND;
|
|
} else {
|
|
goto usage;
|
|
}
|
|
SetTargetImage (image_index, block_size, mem_io,
|
|
endianness, local_addr, pci_addr);
|
|
break;
|
|
case 'o':
|
|
if (tolower (endianness) == 'b') {
|
|
endianness = PB_SLAVE_CSR_BIG_END;
|
|
} else if (tolower (endianness) == 'l') {
|
|
endianness = PB_SLAVE_CSR_TRUE_LEND;
|
|
} else {
|
|
goto usage;
|
|
}
|
|
SetSlaveImage (image_index, block_size, mem_io,
|
|
endianness, local_addr, pci_addr);
|
|
break;
|
|
default:
|
|
goto usage;
|
|
}
|
|
|
|
goto done;
|
|
usage:
|
|
printf ("Usage:\n%s\n", cmdtp->help);
|
|
|
|
done:
|
|
return ret_val;
|
|
}
|