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SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
/*
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* Common internal memory map for some Freescale SoCs
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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*/
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#ifndef __FSL_SEC_H
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#define __FSL_SEC_H
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#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYS_FSL_SEC_LE
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#define sec_in32(a) in_le32(a)
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#define sec_out32(a, v) out_le32(a, v)
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#define sec_in16(a) in_le16(a)
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#define sec_clrbits32 clrbits_le32
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#define sec_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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#define sec_in32(a) in_be32(a)
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#define sec_out32(a, v) out_be32(a, v)
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#define sec_in16(a) in_be16(a)
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#define sec_clrbits32 clrbits_be32
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#define sec_setbits32 setbits_be32
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#else
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#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
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#endif
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/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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typedef struct ccsr_sec {
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u32 res0;
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u32 mcfgr; /* Master CFG Register */
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u8 res1[0x4];
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u32 scfgr;
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struct {
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u32 ms; /* Job Ring LIODN Register, MS */
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u32 ls; /* Job Ring LIODN Register, LS */
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} jrliodnr[4];
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u8 res2[0x2c];
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u32 jrstartr; /* Job Ring Start Register */
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struct {
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u32 ms; /* RTIC LIODN Register, MS */
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u32 ls; /* RTIC LIODN Register, LS */
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} rticliodnr[4];
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u8 res3[0x1c];
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u32 decorr; /* DECO Request Register */
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struct {
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u32 ms; /* DECO LIODN Register, MS */
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u32 ls; /* DECO LIODN Register, LS */
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} decoliodnr[8];
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u8 res4[0x40];
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u32 dar; /* DECO Avail Register */
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u32 drr; /* DECO Reset Register */
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u8 res5[0xe78];
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u32 crnr_ms; /* CHA Revision Number Register, MS */
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u32 crnr_ls; /* CHA Revision Number Register, LS */
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u32 ctpr_ms; /* Compile Time Parameters Register, MS */
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u32 ctpr_ls; /* Compile Time Parameters Register, LS */
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u8 res6[0x10];
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u32 far_ms; /* Fault Address Register, MS */
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u32 far_ls; /* Fault Address Register, LS */
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u32 falr; /* Fault Address LIODN Register */
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u32 fadr; /* Fault Address Detail Register */
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u8 res7[0x4];
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u32 csta; /* CAAM Status Register */
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u8 res8[0x8];
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u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
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u32 ccbvid; /* CHA Cluster Block Version ID Register */
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u32 chavid_ms; /* CHA Version ID Register, MS */
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u32 chavid_ls; /* CHA Version ID Register, LS */
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u32 chanum_ms; /* CHA Number Register, MS */
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u32 chanum_ls; /* CHA Number Register, LS */
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u32 secvid_ms; /* SEC Version ID Register, MS */
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u32 secvid_ls; /* SEC Version ID Register, LS */
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u8 res9[0x6020];
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u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
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u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
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u8 res10[0x8fd8];
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} ccsr_sec_t;
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#define SEC_CTPR_MS_AXI_LIODN 0x08000000
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#define SEC_CTPR_MS_QI 0x02000000
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#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
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#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
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#define SEC_RVID_MA 0x0f000000
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#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
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#define SEC_CHANUM_MS_JRNUM_SHIFT 28
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#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
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#define SEC_CHANUM_MS_DECONUM_SHIFT 24
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#define SEC_SECVID_MS_IPID_MASK 0xffff0000
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#define SEC_SECVID_MS_IPID_SHIFT 16
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#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
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#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
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#define SEC_CCBVID_ERA_MASK 0xff000000
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#define SEC_CCBVID_ERA_SHIFT 24
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#define SEC_SCFGR_RDBENABLE 0x00000400
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#define SEC_SCFGR_VIRT_EN 0x00008000
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#define SEC_CHAVID_LS_RNG_SHIFT 16
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#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
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#endif
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#endif /* __FSL_SEC_H */
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