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The different CPSW sub-system Ethernet ports have different PHY mode
control registers. In order to allow the modes to get configured
independently only the register for the port in question must be
accessed, otherwise we would just be re-configuring the mode for port 1,
while leaving all others at their power-on defaults. Fix this issue by
adding a port-number based offset to the mode control base register
address based on the fact that the control registers for the different
ports are spaced exactly 0x4 bytes apart.
Fixes:
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|---|---|---|
| .. | ||
| am65-cpsw-nuss.c | ||
| cpsw-common.c | ||
| cpsw.c | ||
| cpsw_mdio.c | ||
| cpsw_mdio.h | ||
| davinci_emac.c | ||
| davinci_emac.h | ||
| Kconfig | ||
| keystone_net.c | ||
| Makefile | ||