mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
fd5f2718d3
Add DT property to support reset of TI PHY connected to GEM.
This is present in RevA DT but needs to be extended RevB/1.0/1.1
versions which are built on top.
Fixes: 2b1db7b18c ("arm64: zynqmp: Wire GEM reset gpio")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b093616ddea269043cbbb1e3806644d5a4b23be.1670854455.git.michal.simek@amd.com
46 lines
920 B
Text
46 lines
920 B
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* dts file for Xilinx ZynqMP ZCU102 RevB
|
|
*
|
|
* (C) Copyright 2016 - 2020, Xilinx, Inc.
|
|
*
|
|
* Michal Simek <michal.simek@xilinx.com>
|
|
*/
|
|
|
|
#include "zynqmp-zcu102-revA.dts"
|
|
|
|
/ {
|
|
model = "ZynqMP ZCU102 RevB";
|
|
compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
|
|
};
|
|
|
|
&gem3 {
|
|
phy-handle = <&phyc>;
|
|
mdio: mdio {
|
|
phyc: ethernet-phy@c {
|
|
#phy-cells = <0x1>;
|
|
compatible = "ethernet-phy-id2000.a231";
|
|
reg = <0xc>;
|
|
ti,rx-internal-delay = <0x8>;
|
|
ti,tx-internal-delay = <0xa>;
|
|
ti,fifo-depth = <0x1>;
|
|
ti,dp83867-rxctrl-strap-quirk;
|
|
reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
|
|
};
|
|
/* Cleanup from RevA */
|
|
/delete-node/ ethernet-phy@21;
|
|
};
|
|
};
|
|
|
|
/* Fix collision with u61 */
|
|
&i2c0 {
|
|
i2c-mux@75 {
|
|
i2c@2 {
|
|
max15303@1b { /* u8 */
|
|
compatible = "maxim,max15303";
|
|
reg = <0x1b>;
|
|
};
|
|
/delete-node/ max15303@20;
|
|
};
|
|
};
|
|
};
|