mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
fd6e425be2
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B. Similar to RK3568 the BootRom in RK3588 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1492992 bytes read in 129 ms (11 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x16c800 1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does not match the expected value of 3 (SPINOR) used by other SoCs. Instead a value of 6 is read back, add a new enum value to handle this new bootsource id. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
211 lines
3.2 KiB
Text
211 lines
3.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2023 Collabora Ltd.
|
|
*/
|
|
|
|
#include "rk3588-u-boot.dtsi"
|
|
#include <dt-bindings/pinctrl/rockchip.h>
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
aliases {
|
|
mmc1 = &sdmmc;
|
|
spi0 = &sfc;
|
|
};
|
|
|
|
chosen {
|
|
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
|
|
};
|
|
|
|
vcc5v0_host: vcc5v0-host-regulator {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vcc5v0_host";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&vcc5v0_host_en>;
|
|
vin-supply = <&vcc5v0_sys>;
|
|
};
|
|
};
|
|
|
|
&combphy0_ps {
|
|
status = "okay";
|
|
};
|
|
|
|
&emmc_bus8 {
|
|
bootph-all;
|
|
};
|
|
|
|
&emmc_clk {
|
|
bootph-all;
|
|
};
|
|
|
|
&emmc_cmd {
|
|
bootph-all;
|
|
};
|
|
|
|
&emmc_data_strobe {
|
|
bootph-all;
|
|
};
|
|
|
|
&emmc_rstnout {
|
|
bootph-all;
|
|
};
|
|
|
|
&fspim2_pins {
|
|
bootph-all;
|
|
};
|
|
|
|
&pcie2x1l2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
|
|
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
bootph-all;
|
|
|
|
pcie {
|
|
pcie_reset_h: pcie-reset-h {
|
|
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
pcie2x1l2_pins: pcie2x1l2-pins {
|
|
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
|
|
<3 RK_PD0 4 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
usb {
|
|
vcc5v0_host_en: vcc5v0-host-en {
|
|
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcfg_pull_none {
|
|
bootph-all;
|
|
};
|
|
|
|
&pcfg_pull_up_drv_level_2 {
|
|
bootph-all;
|
|
};
|
|
|
|
&pcfg_pull_up {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdmmc {
|
|
bus-width = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdmmc_bus4 {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdmmc_clk {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdmmc_cmd {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdmmc_det {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdhci {
|
|
cap-mmc-highspeed;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
|
|
};
|
|
|
|
&sfc {
|
|
bootph-pre-ram;
|
|
u-boot,spl-sfc-no-dma;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&fspim2_pins>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
bootph-pre-ram;
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <24000000>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-tx-bus-width = <1>;
|
|
};
|
|
};
|
|
|
|
&uart2m0_xfer {
|
|
bootph-all;
|
|
};
|
|
|
|
&usb_host0_ehci {
|
|
companion = <&usb_host0_ohci>;
|
|
phys = <&u2phy2_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host0_ohci {
|
|
phys = <&u2phy2_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2phy2_grf {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy2 {
|
|
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
|
reset-names = "phy", "apb";
|
|
clock-output-names = "usb480m_phy2";
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy2_host {
|
|
phy-supply = <&vcc5v0_host>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host1_ehci {
|
|
companion = <&usb_host1_ohci>;
|
|
phys = <&u2phy3_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host1_ohci {
|
|
phys = <&u2phy3_host>;
|
|
phy-names = "usb2-phy";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb2phy3_grf {
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy3 {
|
|
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
|
reset-names = "phy", "apb";
|
|
clock-output-names = "usb480m_phy3";
|
|
status = "okay";
|
|
};
|
|
|
|
&u2phy3_host {
|
|
phy-supply = <&vcc5v0_host>;
|
|
status = "okay";
|
|
};
|
|
|