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0238898382
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
425 lines
14 KiB
C
425 lines
14 KiB
C
/*
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* (C) Copyright 2006
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* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* define DEBUG for debug output */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <ppc440.h>
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#include "sdram.h"
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
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defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dlllock.
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+----------------------------------------------------------------------------*/
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static int wait_for_dlllock(void)
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{
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unsigned long val;
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int wait = 0;
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_17);
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val = DDR0_17_DLLLOCKREG_UNLOCKED;
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
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/* dlllockreg bit on */
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return 0;
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else
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wait++;
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}
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debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
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debug("Waiting for dlllockreg bit to raise\n");
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return -1;
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}
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#endif
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#if defined(CONFIG_DDR_DATA_EYE)
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/*-----------------------------------------------------------------------------+
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* wait_for_dram_init_complete.
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+----------------------------------------------------------------------------*/
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int wait_for_dram_init_complete(void)
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{
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unsigned long val;
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int wait = 0;
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/* --------------------------------------------------------------+
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* Wait for 'DRAM initialization complete' bit in status register
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* -------------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_00);
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while (wait != 0xffff) {
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val = mfdcr(ddrcfgd);
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if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
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/* 'DRAM initialization complete' bit */
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return 0;
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else
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wait++;
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}
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debug("DRAM initialization complete bit in status register did not rise\n");
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return -1;
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}
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#define NUM_TRIES 64
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#define NUM_READS 10
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/*-----------------------------------------------------------------------------+
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* denali_core_search_data_eye.
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+----------------------------------------------------------------------------*/
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void denali_core_search_data_eye(unsigned long memory_size)
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{
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int k, j;
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u32 val;
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u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
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u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
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u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
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u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
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volatile u32 *ram_pointer;
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u32 test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
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for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
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/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'wr_dqs_shift'
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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* ----------------------------------------------------------*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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passing_cases = 0;
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for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
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/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
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/* -----------------------------------------------------------+
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* Set 'dll_dqs_delay_X'.
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* ----------------------------------------------------------*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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printf("denali_core_search_data_eye!!!\n");
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printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
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wr_dqs_shift, dll_dqs_delay_X);
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS)
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break;
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}
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/* See if the dll_dqs_delay_X value passed.*/
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if (j < NUM_TRIES) {
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/* Failed */
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passing_cases = 0;
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/* break; */
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} else {
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/* Passed */
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if (passing_cases == 0)
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dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
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passing_cases++;
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if (passing_cases >= max_passing_cases) {
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max_passing_cases = passing_cases;
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wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
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dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
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dll_dqs_delay_X_end_window = dll_dqs_delay_X;
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}
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}
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
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} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
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/* -----------------------------------------------------------+
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* Largest passing window is now detected.
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* ----------------------------------------------------------*/
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/* Compute dll_dqs_delay_X value */
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dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
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wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
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debug("DQS calibration - Window detected:\n");
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debug("max_passing_cases = %d\n", max_passing_cases);
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debug("wr_dqs_shift = %d\n", wr_dqs_shift);
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debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
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debug("dll_dqs_delay_X window = %d - %d\n",
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dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
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/* -----------------------------------------------------------+
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* De-assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
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mtdcr(ddrcfgd, val);
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/* -----------------------------------------------------------+
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* Set 'wr_dqs_shift'
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_09);
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val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
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| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
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mtdcr(ddrcfgd, val);
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debug("DDR0_09=0x%08lx\n", val);
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/* -----------------------------------------------------------+
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* Set 'dqs_out_shift' = wr_dqs_shift + 32
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* ----------------------------------------------------------*/
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dqs_out_shift = wr_dqs_shift + 32;
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mtdcr(ddrcfga, DDR0_22);
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val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
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| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
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mtdcr(ddrcfgd, val);
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debug("DDR0_22=0x%08lx\n", val);
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/* -----------------------------------------------------------+
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* Set 'dll_dqs_delay_X'.
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* ----------------------------------------------------------*/
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/* dll_dqs_delay_0 */
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mtdcr(ddrcfga, DDR0_17);
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val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
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| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_17=0x%08lx\n", val);
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/* dll_dqs_delay_1 to dll_dqs_delay_4 */
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mtdcr(ddrcfga, DDR0_18);
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val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
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| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
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| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_18=0x%08lx\n", val);
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/* dll_dqs_delay_5 to dll_dqs_delay_8 */
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mtdcr(ddrcfga, DDR0_19);
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val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
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| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
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| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
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mtdcr(ddrcfgd, val);
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debug("DDR0_19=0x%08lx\n", val);
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/* -----------------------------------------------------------+
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* Assert 'start' parameter.
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* ----------------------------------------------------------*/
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mtdcr(ddrcfga, DDR0_02);
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val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
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mtdcr(ddrcfgd, val);
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ppcMsync();
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ppcMbar();
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/* -----------------------------------------------------------+
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* Wait for the DCC master delay line to finish calibration
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* ----------------------------------------------------------*/
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if (wait_for_dlllock() != 0) {
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printf("dlllock did not occur !!!\n");
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hang();
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}
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ppcMsync();
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ppcMbar();
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if (wait_for_dram_init_complete() != 0) {
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printf("dram init complete did not occur !!!\n");
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hang();
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}
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udelay(100); /* wait 100us to ensure init is really completed !!! */
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}
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#endif /* CONFIG_DDR_DATA_EYE */
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/*************************************************************************
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*
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* initdram -- 440EPx's DDR controller is a DENALI Core
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*
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************************************************************************/
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long int initdram (int board_type)
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{
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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mtsdram(DDR0_02, 0x00000000);
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mtsdram(DDR0_00, 0x0000190A);
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mtsdram(DDR0_01, 0x01000000);
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mtsdram(DDR0_03, 0x02030602);
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mtsdram(DDR0_04, 0x13030300);
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mtsdram(DDR0_05, 0x0202050E);
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mtsdram(DDR0_06, 0x0104C823);
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mtsdram(DDR0_07, 0x000D0100);
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mtsdram(DDR0_08, 0x02360001);
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mtsdram(DDR0_09, 0x00011D5F);
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mtsdram(DDR0_10, 0x00000300);
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mtsdram(DDR0_11, 0x0027C800);
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mtsdram(DDR0_12, 0x00000003);
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mtsdram(DDR0_14, 0x00000000);
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mtsdram(DDR0_17, 0x19000000);
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mtsdram(DDR0_18, 0x19191919);
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mtsdram(DDR0_19, 0x19191919);
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mtsdram(DDR0_20, 0x0B0B0B0B);
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mtsdram(DDR0_21, 0x0B0B0B0B);
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mtsdram(DDR0_22, 0x00267F0B);
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mtsdram(DDR0_23, 0x00000000);
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mtsdram(DDR0_24, 0x01010002);
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mtsdram(DDR0_26, 0x5B260181);
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mtsdram(DDR0_27, 0x0000682B);
|
|
mtsdram(DDR0_28, 0x00000000);
|
|
mtsdram(DDR0_31, 0x00000000);
|
|
mtsdram(DDR0_42, 0x01000006);
|
|
mtsdram(DDR0_43, 0x050A0200);
|
|
mtsdram(DDR0_44, 0x00000005);
|
|
mtsdram(DDR0_02, 0x00000001);
|
|
|
|
wait_for_dlllock();
|
|
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
|
|
|
#ifdef CONFIG_DDR_DATA_EYE
|
|
/* -----------------------------------------------------------+
|
|
* Perform data eye search if requested.
|
|
* ----------------------------------------------------------*/
|
|
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
|
#endif
|
|
|
|
return (CFG_MBYTES_SDRAM << 20);
|
|
}
|