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https://github.com/AsahiLinux/u-boot
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2a1a579bde
Add clk-programmable driver compatible with common clock framework. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
208 lines
5 KiB
C
208 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Programmable clock support for AT91 architectures.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/clk-programmable.c from Linux.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_PROG "at91-prog-clk"
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#define PROG_ID_MAX 7
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#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
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#define PROG_PRES(_l, _p) (((_p) >> (_l)->pres_shift) & (_l)->pres_mask)
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#define PROG_MAX_RM9200_CSS 3
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struct clk_programmable {
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void __iomem *base;
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const u32 *clk_mux_table;
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const u32 *mux_table;
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const struct clk_programmable_layout *layout;
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u32 num_parents;
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struct clk clk;
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u8 id;
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};
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#define to_clk_programmable(_c) container_of(_c, struct clk_programmable, clk)
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static ulong clk_programmable_get_rate(struct clk *clk)
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{
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struct clk_programmable *prog = to_clk_programmable(clk);
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const struct clk_programmable_layout *layout = prog->layout;
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ulong rate, parent_rate = clk_get_parent_rate(clk);
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unsigned int pckr;
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pmc_read(prog->base, AT91_PMC_PCKR(prog->id), &pckr);
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if (layout->is_pres_direct)
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rate = parent_rate / (PROG_PRES(layout, pckr) + 1);
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else
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rate = parent_rate >> PROG_PRES(layout, pckr);
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return rate;
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}
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static int clk_programmable_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_programmable *prog = to_clk_programmable(clk);
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const struct clk_programmable_layout *layout = prog->layout;
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unsigned int mask = layout->css_mask;
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int index;
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index = at91_clk_mux_val_to_index(prog->clk_mux_table,
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prog->num_parents, parent->id);
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if (index < 0)
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return index;
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index = at91_clk_mux_index_to_val(prog->mux_table, prog->num_parents,
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index);
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if (index < 0)
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return index;
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if (layout->have_slck_mck)
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mask |= AT91_PMC_CSSMCK_MCK;
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if (index > layout->css_mask) {
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if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck)
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return -EINVAL;
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index |= AT91_PMC_CSSMCK_MCK;
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}
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pmc_update_bits(prog->base, AT91_PMC_PCKR(prog->id), mask, index);
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return 0;
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}
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static ulong clk_programmable_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_programmable *prog = to_clk_programmable(clk);
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const struct clk_programmable_layout *layout = prog->layout;
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ulong parent_rate = clk_get_parent_rate(clk);
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ulong div = parent_rate / rate;
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int shift = 0;
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if (!parent_rate || !div)
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return -EINVAL;
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if (layout->is_pres_direct) {
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shift = div - 1;
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if (shift > layout->pres_mask)
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return -EINVAL;
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} else {
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shift = fls(div) - 1;
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if (div != (1 << shift))
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return -EINVAL;
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if (shift >= layout->pres_mask)
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return -EINVAL;
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}
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pmc_update_bits(prog->base, AT91_PMC_PCKR(prog->id),
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layout->pres_mask << layout->pres_shift,
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shift << layout->pres_shift);
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if (layout->is_pres_direct)
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return (parent_rate / shift + 1);
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return parent_rate >> shift;
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}
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static const struct clk_ops programmable_ops = {
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.get_rate = clk_programmable_get_rate,
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.set_parent = clk_programmable_set_parent,
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.set_rate = clk_programmable_set_rate,
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};
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struct clk *at91_clk_register_programmable(void __iomem *base, const char *name,
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const char *const *parent_names, u8 num_parents, u8 id,
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const struct clk_programmable_layout *layout,
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const u32 *clk_mux_table, const u32 *mux_table)
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{
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struct clk_programmable *prog;
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struct clk *clk;
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u32 val, tmp;
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int ret;
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if (!base || !name || !parent_names || !num_parents ||
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!layout || !clk_mux_table || !mux_table || id > PROG_ID_MAX)
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return ERR_PTR(-EINVAL);
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prog = kzalloc(sizeof(*prog), GFP_KERNEL);
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if (!prog)
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return ERR_PTR(-ENOMEM);
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prog->id = id;
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prog->layout = layout;
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prog->base = base;
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prog->clk_mux_table = clk_mux_table;
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prog->mux_table = mux_table;
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prog->num_parents = num_parents;
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pmc_read(prog->base, AT91_PMC_PCKR(prog->id), &tmp);
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val = tmp & prog->layout->css_mask;
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if (layout->have_slck_mck && (tmp & AT91_PMC_CSSMCK_MCK) && !val)
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ret = PROG_MAX_RM9200_CSS + 1;
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else
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ret = at91_clk_mux_val_to_index(prog->mux_table,
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prog->num_parents, val);
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if (ret < 0) {
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kfree(prog);
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return ERR_PTR(ret);
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}
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clk = &prog->clk;
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clk->flags = CLK_GET_RATE_NOCACHE;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_PROG, name,
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parent_names[ret]);
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if (ret) {
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kfree(prog);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_prog_clk) = {
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.name = UBOOT_DM_CLK_AT91_PROG,
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.id = UCLASS_CLK,
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.ops = &programmable_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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const struct clk_programmable_layout at91rm9200_programmable_layout = {
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.pres_mask = 0x7,
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.pres_shift = 2,
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.css_mask = 0x3,
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.have_slck_mck = 0,
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.is_pres_direct = 0,
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};
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const struct clk_programmable_layout at91sam9g45_programmable_layout = {
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.pres_mask = 0x7,
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.pres_shift = 2,
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.css_mask = 0x3,
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.have_slck_mck = 1,
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.is_pres_direct = 0,
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};
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const struct clk_programmable_layout at91sam9x5_programmable_layout = {
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.pres_mask = 0x7,
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.pres_shift = 4,
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.css_mask = 0x7,
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.have_slck_mck = 0,
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.is_pres_direct = 0,
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};
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