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https://github.com/AsahiLinux/u-boot
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c1dc8473fa
Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
226 lines
4.7 KiB
C
226 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology.
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*/
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#include <common.h>
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#include <dm.h>
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#include <spi.h>
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#include <clk.h>
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#include <asm/gpio.h>
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#include <linux/iopoll.h>
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#define MAX_DIV 127
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/* Register offsets */
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#define PSPI_DATA 0
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#define PSPI_CTL1 2
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#define PSPI_STAT 4
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/* PSPI_CTL1 fields */
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#define PSPI_CTL1_SPIEN BIT(0)
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#define PSPI_CTL1_SCM BIT(7)
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#define PSPI_CTL1_SCIDL BIT(8)
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#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9)
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#define PSPI_CTL1_SCDV_SHIFT 9
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/* PSPI_STAT fields */
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#define PSPI_STAT_BSY BIT(0)
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#define PSPI_STAT_RBF BIT(1)
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struct npcm_pspi_priv {
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void __iomem *base;
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struct clk clk;
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struct gpio_desc cs_gpio;
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u32 max_hz;
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};
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static inline void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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dm_gpio_set_value(&priv->cs_gpio, 0);
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}
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static inline void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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dm_gpio_set_value(&priv->cs_gpio, 1);
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}
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static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv)
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{
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u16 val;
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val = readw(priv->base + PSPI_CTL1);
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val |= PSPI_CTL1_SPIEN;
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writew(val, priv->base + PSPI_CTL1);
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}
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static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv)
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{
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u16 val;
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val = readw(priv->base + PSPI_CTL1);
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val &= ~PSPI_CTL1_SPIEN;
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writew(val, priv->base + PSPI_CTL1);
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}
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static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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void __iomem *base = priv->base;
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const u8 *tx = dout;
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u8 *rx = din;
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u32 bytes = bitlen / 8;
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u8 tmp;
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u32 val;
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int i, ret = 0;
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npcm_pspi_enable(priv);
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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for (i = 0; i < bytes; i++) {
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/* Making sure we can write */
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ret = readb_poll_timeout(base + PSPI_STAT, val,
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!(val & PSPI_STAT_BSY),
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1000000);
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if (ret < 0)
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break;
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if (tx)
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writeb(*tx++, base + PSPI_DATA);
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else
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writeb(0, base + PSPI_DATA);
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/* Wait till write completed */
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ret = readb_poll_timeout(base + PSPI_STAT, val,
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!(val & PSPI_STAT_BSY),
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1000000);
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if (ret < 0)
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break;
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/* Wait till read buffer full */
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ret = readb_poll_timeout(base + PSPI_STAT, val,
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(val & PSPI_STAT_RBF),
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1000000);
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if (ret < 0)
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break;
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tmp = readb(base + PSPI_DATA);
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if (rx)
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*rx++ = tmp;
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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npcm_pspi_disable(priv);
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return ret;
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}
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static int npcm_pspi_set_speed(struct udevice *bus, uint speed)
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{
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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ulong apb_clock;
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u32 divisor;
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u16 val;
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apb_clock = clk_get_rate(&priv->clk);
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if (!apb_clock)
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return -EINVAL;
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if (speed > priv->max_hz)
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speed = priv->max_hz;
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divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1);
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if (divisor > MAX_DIV)
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divisor = MAX_DIV;
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val = readw(priv->base + PSPI_CTL1);
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val &= ~PSPI_CTL1_SCDV_MASK;
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val |= divisor << PSPI_CTL1_SCDV_SHIFT;
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writew(val, priv->base + PSPI_CTL1);
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debug("%s: apb_clock=%lu speed=%d divisor=%u\n",
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__func__, apb_clock, speed, divisor);
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return 0;
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}
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static int npcm_pspi_set_mode(struct udevice *bus, uint mode)
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{
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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u16 pspi_mode, val;
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switch (mode & (SPI_CPOL | SPI_CPHA)) {
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case SPI_MODE_0:
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pspi_mode = 0;
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break;
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case SPI_MODE_1:
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pspi_mode = PSPI_CTL1_SCM;
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break;
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case SPI_MODE_2:
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pspi_mode = PSPI_CTL1_SCIDL;
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break;
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case SPI_MODE_3:
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pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM;
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break;
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default:
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break;
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}
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val = readw(priv->base + PSPI_CTL1);
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val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM);
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val |= pspi_mode;
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writew(val, priv->base + PSPI_CTL1);
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return 0;
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}
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static int npcm_pspi_probe(struct udevice *bus)
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{
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struct npcm_pspi_priv *priv = dev_get_priv(bus);
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int node = dev_of_offset(bus);
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int ret;
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret < 0)
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return ret;
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priv->base = dev_read_addr_ptr(bus);
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priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
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gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
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&priv->cs_gpio, GPIOD_IS_OUT);
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return 0;
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}
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static const struct dm_spi_ops npcm_pspi_ops = {
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.xfer = npcm_pspi_xfer,
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.set_speed = npcm_pspi_set_speed,
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.set_mode = npcm_pspi_set_mode,
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};
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static const struct udevice_id npcm_pspi_ids[] = {
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{ .compatible = "nuvoton,npcm845-pspi"},
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{ .compatible = "nuvoton,npcm750-pspi"},
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{ }
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};
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U_BOOT_DRIVER(npcm_pspi) = {
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.name = "npcm_pspi",
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.id = UCLASS_SPI,
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.of_match = npcm_pspi_ids,
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.ops = &npcm_pspi_ops,
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.priv_auto = sizeof(struct npcm_pspi_priv),
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.probe = npcm_pspi_probe,
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};
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