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113 lines
3.6 KiB
Text
113 lines
3.6 KiB
Text
The pinctrl driver enables Marvell Armada 8K SoCs to configure the multi-purpose
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pins (mpp) to a specific function.
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A Marvell SoC pin configuration node is a node of a group of pins which can
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be used for a specific device or function. Each node requires one or more
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mpp pins or group of pins and a mpp function common to all pins.
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Required properties for the pinctrl driver:
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- compatible: "marvell,mvebu-pinctrl",
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"marvell,ap806-pinctrl",
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"marvell,armada-7k-pinctrl",
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"marvell,armada-8k-cpm-pinctrl",
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"marvell,armada-8k-cps-pinctrl"
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- bank-name: A string defining the pinc controller bank name
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- reg: A pair of values defining the pin controller base address
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and the address space
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- pin-count: Numeric value defining the amount of multi purpose pins
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included in this bank
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- max-func: Numeric value defining the maximum function value for
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pins in this bank
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- pin-func: Array of pin function values for every pin in the bank.
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When the function value for a specific pin equal 0xFF,
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the pin configuration is skipped and a default function
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value is used for this pin.
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The A8K is a hybrid SoC that contains several silicon dies interconnected in
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a single package. Each such die may have a separate pin controller.
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Example:
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/ {
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ap806 {
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config-space {
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pinctl: pinctl@6F4000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,ap806-pinctrl";
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bank-name ="apn-806";
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reg = <0x6F4000 0x10>;
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pin-count = <20>;
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max-func = <3>;
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/* MPP Bus:
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* SPI0 [0-3]
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* I2C0 [4-5]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 3 3 3 3 3 3 0 0 0 0
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0 3 0 0 0 0 0 0 0 3>;
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};
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};
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};
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cp110-master {
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config-space {
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cpm_pinctl: pinctl@44000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,armada-7k-pinctrl",
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"marvell,armada-8k-cpm-pinctrl";
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bank-name ="cp0-110";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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/* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32,34] SMI
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* [31] GPIO: push button/Wake
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* [35-36] GPIO
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* [37-38] I2C
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* [40-41] SATA[0/1]_PRESENT_ACTIVEn
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* [42-43] XSMI
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* [44-55] RGMII1
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* [56-62] SD
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0 7 0 7 0 0 2 2 0
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0 0 8 8 1 1 1 1 1 1
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1 1 1 1 1 1 0xE 0xE 0xE 0xE
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0xE 0xE 0xE>;
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};
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};
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};
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cp110-slave {
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config-space {
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cps_pinctl: pinctl@44000 {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,armada-8k-cps-pinctrl";
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bank-name ="cp1-110";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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/* MPP Bus:
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* [0-11] RGMII0
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* [27,31] GE_MDIO/MDC
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
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0x3 0x3 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff
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0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff>;
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};
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};
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};
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}
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