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https://github.com/AsahiLinux/u-boot
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01a701994b
Add initial support for STM32MP2 SoCs family. SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html Migrate all MP1 related code into stm32mp1/ directory Create stm32mp2 directory dedicated for STM32MP2 SoCs. Common code to MP1, MP13 and MP25 is kept into arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu(). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
194 lines
3.8 KiB
C
194 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <common.h>
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#include <log.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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/* SYSCFG register */
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#define SYSCFG_DEVICEID_OFFSET 0x6400
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#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
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#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
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#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
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#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
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/* Device Part Number (RPN) = OTP9 */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(31, 0)
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/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
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* - 000: Custom package
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* - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
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* - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
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* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
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* - others: Reserved
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*/
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#define PKG_SHIFT 0
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#define PKG_MASK GENMASK(2, 0)
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static u32 read_deviceid(void)
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{
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void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
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}
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u32 get_cpu_dev(void)
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{
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return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
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}
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u32 get_cpu_rev(void)
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{
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return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
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}
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/* Get Device Part Number (RPN) from OTP */
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u32 get_cpu_type(void)
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{
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return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
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}
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/* Get Package options from OTP */
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u32 get_cpu_package(void)
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{
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return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
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}
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int get_eth_nb(void)
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{
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int nb_eth;
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switch (get_cpu_type()) {
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case CPU_STM32MP257Fxx:
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fallthrough;
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case CPU_STM32MP257Dxx:
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fallthrough;
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case CPU_STM32MP257Cxx:
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fallthrough;
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case CPU_STM32MP257Axx:
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nb_eth = 5; /* dual ETH with TSN support */
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break;
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case CPU_STM32MP253Fxx:
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fallthrough;
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case CPU_STM32MP253Dxx:
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fallthrough;
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case CPU_STM32MP253Cxx:
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fallthrough;
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case CPU_STM32MP253Axx:
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nb_eth = 2; /* dual ETH */
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break;
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case CPU_STM32MP251Fxx:
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fallthrough;
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case CPU_STM32MP251Dxx:
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fallthrough;
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case CPU_STM32MP251Cxx:
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fallthrough;
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case CPU_STM32MP251Axx:
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nb_eth = 1; /* single ETH */
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break;
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default:
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nb_eth = 0;
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break;
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}
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return nb_eth;
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}
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void get_soc_name(char name[SOC_NAME_SIZE])
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{
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char *cpu_s, *cpu_r, *package;
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cpu_s = "????";
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cpu_r = "?";
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package = "??";
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if (get_cpu_dev() == CPU_DEV_STM32MP25) {
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switch (get_cpu_type()) {
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case CPU_STM32MP257Fxx:
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cpu_s = "257F";
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break;
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case CPU_STM32MP257Dxx:
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cpu_s = "257D";
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break;
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case CPU_STM32MP257Cxx:
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cpu_s = "257C";
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break;
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case CPU_STM32MP257Axx:
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cpu_s = "257A";
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break;
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case CPU_STM32MP255Fxx:
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cpu_s = "255F";
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break;
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case CPU_STM32MP255Dxx:
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cpu_s = "255D";
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break;
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case CPU_STM32MP255Cxx:
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cpu_s = "255C";
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break;
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case CPU_STM32MP255Axx:
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cpu_s = "255A";
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break;
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case CPU_STM32MP253Fxx:
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cpu_s = "253F";
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break;
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case CPU_STM32MP253Dxx:
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cpu_s = "253D";
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break;
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case CPU_STM32MP253Cxx:
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cpu_s = "253C";
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break;
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case CPU_STM32MP253Axx:
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cpu_s = "253A";
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break;
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case CPU_STM32MP251Fxx:
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cpu_s = "251F";
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break;
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case CPU_STM32MP251Dxx:
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cpu_s = "251D";
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break;
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case CPU_STM32MP251Cxx:
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cpu_s = "251C";
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break;
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case CPU_STM32MP251Axx:
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cpu_s = "251A";
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break;
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default:
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cpu_s = "25??";
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break;
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}
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/* REVISION */
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switch (get_cpu_rev()) {
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case CPU_REV1:
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cpu_r = "A";
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break;
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default:
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break;
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}
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/* PACKAGE */
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switch (get_cpu_package()) {
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case STM32MP25_PKG_CUSTOM:
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package = "XX";
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break;
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case STM32MP25_PKG_AL_TBGA361:
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package = "AL";
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break;
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case STM32MP25_PKG_AK_TBGA424:
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package = "AK";
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break;
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case STM32MP25_PKG_AI_TBGA436:
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package = "AI";
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break;
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default:
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break;
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}
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}
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
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}
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