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01a701994b
Add initial support for STM32MP2 SoCs family. SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html Migrate all MP1 related code into stm32mp1/ directory Create stm32mp2 directory dedicated for STM32MP2 SoCs. Common code to MP1, MP13 and MP25 is kept into arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu(). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#define MP2_MEM_MAP_MAX 10
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#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
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(CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
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#error "invalid CONFIG_TEXT_BASE value"
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#endif
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struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
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{
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/* PCIe */
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.virt = 0x10000000UL,
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.phys = 0x10000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
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.virt = 0x20000000UL,
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.phys = 0x20000000UL,
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.size = 0x00200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Peripherals: alias1 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OSPI and FMC: memory-map area */
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.virt = 0x60000000UL,
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.phys = 0x60000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/*
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* DDR = STM32_DDR_BASE / STM32_DDR_SIZE
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* the beginning of DDR (before CONFIG_TEXT_BASE) is not
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* mapped, protected by RIF and reserved for other firmware
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* (OP-TEE / TF-M / Cube M33)
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*/
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.virt = CONFIG_TEXT_BASE,
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.phys = CONFIG_TEXT_BASE,
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.size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = stm32mp2_mem_map;
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