mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 03:03:05 +00:00
ed7bda5710
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright 2021 NXP
|
|
*/
|
|
|
|
#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
|
|
#define DT_BINDING_PCC_RESET_IMX8ULP_H
|
|
|
|
/* PCC3 */
|
|
#define PCC3_WDOG3_SWRST 0
|
|
#define PCC3_WDOG4_SWRST 1
|
|
#define PCC3_LPIT1_SWRST 2
|
|
#define PCC3_TPM4_SWRST 3
|
|
#define PCC3_TPM5_SWRST 4
|
|
#define PCC3_FLEXIO1_SWRST 5
|
|
#define PCC3_I3C2_SWRST 6
|
|
#define PCC3_LPI2C4_SWRST 7
|
|
#define PCC3_LPI2C5_SWRST 8
|
|
#define PCC3_LPUART4_SWRST 9
|
|
#define PCC3_LPUART5_SWRST 10
|
|
#define PCC3_LPSPI4_SWRST 11
|
|
#define PCC3_LPSPI5_SWRST 12
|
|
|
|
/* PCC4 */
|
|
#define PCC4_FLEXSPI2_SWRST 0
|
|
#define PCC4_TPM6_SWRST 1
|
|
#define PCC4_TPM7_SWRST 2
|
|
#define PCC4_LPI2C6_SWRST 3
|
|
#define PCC4_LPI2C7_SWRST 4
|
|
#define PCC4_LPUART6_SWRST 5
|
|
#define PCC4_LPUART7_SWRST 6
|
|
#define PCC4_SAI4_SWRST 7
|
|
#define PCC4_SAI5_SWRST 8
|
|
#define PCC4_USDHC0_SWRST 9
|
|
#define PCC4_USDHC1_SWRST 10
|
|
#define PCC4_USDHC2_SWRST 11
|
|
#define PCC4_USB0_SWRST 12
|
|
#define PCC4_USB0_PHY_SWRST 13
|
|
#define PCC4_USB1_SWRST 14
|
|
#define PCC4_USB1_PHY_SWRST 15
|
|
#define PCC4_ENET_SWRST 16
|
|
|
|
/* PCC5 */
|
|
#define PCC5_TPM8_SWRST 0
|
|
#define PCC5_SAI6_SWRST 1
|
|
#define PCC5_SAI7_SWRST 2
|
|
#define PCC5_SPDIF_SWRST 3
|
|
#define PCC5_ISI_SWRST 4
|
|
#define PCC5_CSI_REGS_SWRST 5
|
|
#define PCC5_CSI_SWRST 6
|
|
#define PCC5_DSI_SWRST 7
|
|
#define PCC5_WDOG5_SWRST 8
|
|
#define PCC5_EPDC_SWRST 9
|
|
#define PCC5_PXP_SWRST 10
|
|
#define PCC5_GPU2D_SWRST 11
|
|
#define PCC5_GPU3D_SWRST 12
|
|
#define PCC5_DC_NANO_SWRST 13
|
|
|
|
#endif /*DT_BINDING_RESET_IMX8ULP_H */
|