mirror of
https://github.com/AsahiLinux/u-boot
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c726fc01cf
There is a number of users that use uclass_first_device to access the first and (assumed) only device in uclass. Some check the return value of uclass_first_device and also that a device was returned which is exactly what uclass_first_device_err does. Some are not checking that a device was returned and can potentially crash if no device exists in the uclass. Finally there is one that returns NULL on error either way. Convert all of these to use uclass_first_device_err instead, the return value will be removed from uclass_first_device in a later patch. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
110 lines
2.1 KiB
C
110 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* Based on code from coreboot src/soc/intel/broadwell/cpu.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <cpu.h>
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#include <event.h>
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#include <init.h>
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#include <log.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/cpu_common.h>
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#include <asm/global_data.h>
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#include <asm/intel_regs.h>
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#include <asm/lpc_common.h>
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#include <asm/msr.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/turbo.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/rcb.h>
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static int broadwell_init_cpu(void *ctx, struct event *event)
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{
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struct udevice *dev;
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int ret;
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/* Start up the LPC so we have serial */
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ret = uclass_first_device_err(UCLASS_LPC, &dev);
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if (ret)
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return ret;
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ret = cpu_set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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EVENT_SPY(EVT_DM_POST_INIT, broadwell_init_cpu);
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void set_max_freq(void)
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{
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msr_t msr, perf_ctl;
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if (cpu_config_tdp_levels()) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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perf_ctl.hi = 0;
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msr_write(MSR_IA32_PERF_CTL, perf_ctl);
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debug("CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_TPL
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/* Do a mini-init if TPL has already done the full init */
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return x86_cpu_reinit_f();
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#else
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return x86_cpu_init_f();
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#endif
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}
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int checkcpu(void)
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{
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int ret;
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set_max_freq();
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ret = cpu_common_init();
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if (ret)
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return ret;
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gd->arch.pei_boot_mode = PEI_BOOT_NONE;
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return 0;
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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/* com1 / com2 decode range */
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pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
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pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
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}
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