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https://github.com/AsahiLinux/u-boot
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88a9e58b99
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use a base variable with uintptr_t size in the rk_pwm.c file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
220 lines
5.1 KiB
C
220 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <log.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/pwm.h>
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#include <linux/bitops.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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unsigned int prescaler;
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bool supports_polarity;
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bool supports_lock;
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u32 enable_conf;
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u32 enable_conf_mask;
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};
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struct rk_pwm_priv {
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uintptr_t base;
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ulong freq;
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u32 conf_polarity;
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const struct rockchip_pwm_data *data;
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};
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static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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if (!priv->data->supports_polarity) {
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debug("%s: Do not support polarity\n", __func__);
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return 0;
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}
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debug("%s: polarity=%u\n", __func__, polarity);
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if (polarity)
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priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
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else
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priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
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return 0;
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}
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static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
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uint duty_ns)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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const struct rockchip_pwm_regs *regs = &priv->data->regs;
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unsigned long period, duty;
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u32 ctrl;
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debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
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ctrl = readl(priv->base + regs->ctrl);
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/*
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* Lock the period and duty of previous configuration, then
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* change the duty and period, that would not be effective.
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*/
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if (priv->data->supports_lock) {
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ctrl |= PWM_LOCK;
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writel(ctrl, priv->base + regs->ctrl);
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}
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period = lldiv((uint64_t)priv->freq * period_ns,
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priv->data->prescaler * 1000000000);
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duty = lldiv((uint64_t)priv->freq * duty_ns,
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priv->data->prescaler * 1000000000);
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writel(period, priv->base + regs->period);
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writel(duty, priv->base + regs->duty);
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if (priv->data->supports_polarity) {
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ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
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ctrl |= priv->conf_polarity;
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}
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/*
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* Unlock and set polarity at the same time,
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* the configuration of duty, period and polarity
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* would be effective together at next period.
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*/
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if (priv->data->supports_lock)
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ctrl &= ~PWM_LOCK;
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writel(ctrl, priv->base + regs->ctrl);
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debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
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return 0;
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}
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static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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const struct rockchip_pwm_regs *regs = &priv->data->regs;
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u32 ctrl;
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debug("%s: Enable '%s'\n", __func__, dev->name);
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ctrl = readl(priv->base + regs->ctrl);
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ctrl &= ~priv->data->enable_conf_mask;
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if (enable)
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ctrl |= priv->data->enable_conf;
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else
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ctrl &= ~priv->data->enable_conf;
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writel(ctrl, priv->base + regs->ctrl);
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return 0;
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}
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static int rk_pwm_of_to_plat(struct udevice *dev)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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return 0;
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}
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static int rk_pwm_probe(struct udevice *dev)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret = 0;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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debug("%s get clock fail!\n", __func__);
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return -EINVAL;
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}
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priv->freq = clk_get_rate(&clk);
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priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
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if (priv->data->supports_polarity)
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priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
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return 0;
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}
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static const struct pwm_ops rk_pwm_ops = {
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.set_invert = rk_pwm_set_invert,
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.set_config = rk_pwm_set_config,
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.set_enable = rk_pwm_set_enable,
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};
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static const struct rockchip_pwm_data pwm_data_v1 = {
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.regs = {
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.duty = 0x04,
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.period = 0x08,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 2,
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.supports_polarity = false,
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.supports_lock = false,
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.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
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.enable_conf_mask = BIT(1) | BIT(3),
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};
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static const struct rockchip_pwm_data pwm_data_v2 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = false,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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};
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static const struct rockchip_pwm_data pwm_data_v3 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = true,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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};
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static const struct udevice_id rk_pwm_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
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{ .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
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{ .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
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{ }
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};
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U_BOOT_DRIVER(rk_pwm) = {
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.name = "rk_pwm",
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.id = UCLASS_PWM,
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.of_match = rk_pwm_ids,
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.ops = &rk_pwm_ops,
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.of_to_plat = rk_pwm_of_to_plat,
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.probe = rk_pwm_probe,
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.priv_auto = sizeof(struct rk_pwm_priv),
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};
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