mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
e053ccf6ef
This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
173 lines
2.8 KiB
Text
173 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2022 MediaTek Inc.
|
|
* Author: Sam Shih <sam.shih@mediatek.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "mt7981.dtsi"
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
model = "mt7981-rfb";
|
|
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
|
|
chosen {
|
|
stdout-path = &uart0;
|
|
tick-timer = &timer0;
|
|
};
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_pins>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ð {
|
|
status = "okay";
|
|
mediatek,gmac-id = <0>;
|
|
phy-mode = "sgmii";
|
|
mediatek,switch = "mt7531";
|
|
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
&pinctrl {
|
|
spi_flash_pins: spi0-pins-func-1 {
|
|
mux {
|
|
function = "flash";
|
|
groups = "spi0", "spi0_wp_hold";
|
|
};
|
|
|
|
conf-pu {
|
|
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
|
drive-strength = <MTK_DRIVE_8mA>;
|
|
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
|
};
|
|
|
|
conf-pd {
|
|
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
|
drive-strength = <MTK_DRIVE_8mA>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
|
};
|
|
};
|
|
|
|
spi2_flash_pins: spi2-spi2-pins {
|
|
mux {
|
|
function = "spi";
|
|
groups = "spi2", "spi2_wp_hold";
|
|
};
|
|
|
|
conf-pu {
|
|
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
|
drive-strength = <MTK_DRIVE_8mA>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
|
};
|
|
|
|
conf-pd {
|
|
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
|
drive-strength = <MTK_DRIVE_8mA>;
|
|
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
|
};
|
|
};
|
|
|
|
spic_pins: spi1-pins-func-1 {
|
|
mux {
|
|
function = "spi";
|
|
groups = "spi1_1";
|
|
};
|
|
};
|
|
|
|
uart1_pins: spi1-pins-func-3 {
|
|
mux {
|
|
function = "uart";
|
|
groups = "uart1_2";
|
|
};
|
|
};
|
|
|
|
/* pin15 as pwm0 */
|
|
one_pwm_pins: one-pwm-pins {
|
|
mux {
|
|
function = "pwm";
|
|
groups = "pwm0_1";
|
|
};
|
|
};
|
|
|
|
/* pin15 as pwm0 and pin14 as pwm1 */
|
|
two_pwm_pins: two-pwm-pins {
|
|
mux {
|
|
function = "pwm";
|
|
groups = "pwm0_1", "pwm1_0";
|
|
};
|
|
};
|
|
|
|
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
|
|
three_pwm_pins: three-pwm-pins {
|
|
mux {
|
|
function = "pwm";
|
|
groups = "pwm0_1", "pwm1_0", "pwm2";
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi_flash_pins>;
|
|
status = "okay";
|
|
must_tx;
|
|
enhance_timing;
|
|
dma_ext;
|
|
ipm_design;
|
|
support_quad;
|
|
tick_dly = <2>;
|
|
sample_sel = <0>;
|
|
|
|
spi_nand@0 {
|
|
compatible = "spi-nand";
|
|
reg = <0>;
|
|
spi-max-frequency = <52000000>;
|
|
};
|
|
};
|
|
|
|
&spi2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_flash_pins>;
|
|
status = "okay";
|
|
must_tx;
|
|
enhance_timing;
|
|
dma_ext;
|
|
ipm_design;
|
|
support_quad;
|
|
tick_dly = <2>;
|
|
sample_sel = <0>;
|
|
|
|
spi_nor@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <52000000>;
|
|
};
|
|
};
|
|
|
|
&pwm {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&two_pwm_pins>;
|
|
status = "okay";
|
|
};
|
|
|
|
&watchdog {
|
|
status = "disabled";
|
|
};
|