mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
1bc527e8f4
Support added for HS and GP boot binaries for AM64x.
HS-SE:
* tiboot3-am64x_sr2-hs-evm.bin
* tispl.bin
* u-boot.img
HS-FS:
* tiboot3-am64x_sr2-hs-fs-evm.bin
* tispl.bin
* u-boot.img
GP:
* tiboot3.bin --> tiboot3-am64x-gp-evm.bin
* tispl.bin_unsigned
* u-boot.img_unsigned
Note that the bootflow followed by AM64x requires:
tiboot3.bin:
* R5 SPL
* R5 SPL dtbs
* sysfw
* board-cfg
* pm-cfg
* sec-cfg
* rm-cfg
tispl.bin:
* ATF
* OP-TEE
* A53 SPL
* A53 SPL dtbs
u-boot.img:
* A53 U-Boot
* A53 U-Boot dtbs
Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
242 lines
3.7 KiB
Text
242 lines
3.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am64x-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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mmc1 = &sdhci1;
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};
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memory@80000000 {
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bootph-pre-ram;
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};
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};
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&cbass_main{
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bootph-pre-ram;
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timer1: timer@2400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x2400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <200000000>;
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bootph-pre-ram;
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};
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};
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&main_conf {
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bootph-pre-ram;
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chipid@14 {
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bootph-pre-ram;
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};
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};
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&main_pmx0 {
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bootph-pre-ram;
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main_i2c0_pins_default: main-i2c0-pins-default {
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bootph-pre-ram;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
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AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
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>;
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};
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};
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&main_i2c0 {
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bootph-pre-ram;
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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tps65219: pmic@30 {
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compatible = "ti,tps65219";
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reg = <0x30>;
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regulators {
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buck1_reg: buck1 {
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regulator-name = "VDD_CORE";
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <750000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck2_reg: buck2 {
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regulator-name = "VCC1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck3_reg: buck3 {
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regulator-name = "VDD_LPDDR4";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: ldo1 {
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regulator-name = "VDDSHV_SD_IO_PMIC";
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regulator-min-microvolt = <33000000>;
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regulator-max-microvolt = <33000000>;
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};
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ldo2_reg: ldo2 {
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regulator-name = "VDDAR_CORE";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: ldo3 {
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regulator-name = "VDDA_1V8";
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regulator-min-microvolt = <18000000>;
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regulator-max-microvolt = <18000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: ldo4 {
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regulator-name = "VDD_PHY_2V5";
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regulator-min-microvolt = <25000000>;
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regulator-max-microvolt = <25000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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&main_uart0 {
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bootph-pre-ram;
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};
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&dmss {
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bootph-pre-ram;
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};
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&secure_proxy_main {
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bootph-pre-ram;
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};
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&dmsc {
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bootph-pre-ram;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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bootph-pre-ram;
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};
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};
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&k3_pds {
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bootph-pre-ram;
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};
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&k3_clks {
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bootph-pre-ram;
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};
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&k3_reset {
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bootph-pre-ram;
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};
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&sdhci0 {
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status = "disabled";
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bootph-pre-ram;
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};
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&sdhci1 {
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bootph-pre-ram;
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};
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&main_mmc1_pins_default {
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bootph-pre-ram;
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};
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&cpsw3g {
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reg = <0x0 0x8000000 0x0 0x200000>,
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<0x0 0x43000200 0x0 0x8>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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bootph-pre-ram;
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cpsw-phy-sel@04044 {
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compatible = "ti,am64-phy-gmii-sel";
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reg = <0x0 0x43004044 0x0 0x8>;
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bootph-pre-ram;
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};
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ethernet-ports {
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bootph-pre-ram;
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};
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};
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&cpsw_port2 {
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bootph-pre-ram;
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};
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&main_bcdma {
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bootph-pre-ram;
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};
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&main_pktdma {
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bootph-pre-ram;
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};
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&rgmii1_pins_default {
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bootph-pre-ram;
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};
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&rgmii2_pins_default {
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bootph-pre-ram;
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};
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&mdio1_pins_default {
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bootph-pre-ram;
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};
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&cpsw3g_phy1 {
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bootph-pre-ram;
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};
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&main_usb0_pins_default {
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bootph-pre-ram;
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};
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&serdes_ln_ctrl {
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u-boot,mux-autoprobe;
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};
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&usbss0 {
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bootph-pre-ram;
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};
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&usb0 {
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dr_mode = "host";
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bootph-pre-ram;
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};
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&serdes_wiz0 {
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bootph-pre-ram;
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};
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&serdes0_usb_link {
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bootph-pre-ram;
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};
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&serdes0 {
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bootph-pre-ram;
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};
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&serdes_refclk {
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bootph-pre-ram;
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};
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