mirror of
https://github.com/AsahiLinux/u-boot
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29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
233 lines
5.1 KiB
C
233 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Anup Patel <anup@brainfault.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <watchdog.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <serial.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_TXFIFO_FULL 0x80000000
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#define UART_RXFIFO_EMPTY 0x80000000
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#define UART_RXFIFO_DATA 0x000000ff
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#define UART_TXCTRL_TXEN 0x1
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#define UART_RXCTRL_RXEN 0x1
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/* IP register */
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#define UART_IP_RXWM 0x2
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struct uart_sifive {
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u32 txfifo;
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u32 rxfifo;
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u32 txctrl;
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u32 rxctrl;
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u32 ie;
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u32 ip;
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u32 div;
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};
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struct sifive_uart_plat {
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unsigned long clock;
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struct uart_sifive *regs;
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};
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/**
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* Find minimum divisor divides in_freq to max_target_hz;
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* Based on uart driver n SiFive FSBL.
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*
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* f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
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* The nearest integer solution requires rounding up as to not exceed
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* max_target_hz.
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* div = ceil(f_in / f_baud) - 1
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* = floor((f_in - 1 + f_baud) / f_baud) - 1
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* This should not overflow as long as (f_in - 1 + f_baud) does not exceed
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* 2^32 - 1, which is unlikely since we represent frequencies in kHz.
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*/
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static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
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unsigned long max_target_hz)
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{
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unsigned long quotient =
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(in_freq + max_target_hz - 1) / (max_target_hz);
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/* Avoid underflow */
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if (quotient == 0)
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return 0;
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else
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return quotient - 1;
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}
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/* Set up the baud rate in gd struct */
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static void _sifive_serial_setbrg(struct uart_sifive *regs,
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unsigned long clock, unsigned long baud)
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{
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writel((uart_min_clk_divisor(clock, baud)), ®s->div);
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}
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static void _sifive_serial_init(struct uart_sifive *regs)
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{
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writel(UART_TXCTRL_TXEN, ®s->txctrl);
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writel(UART_RXCTRL_RXEN, ®s->rxctrl);
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writel(0, ®s->ie);
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}
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static int _sifive_serial_putc(struct uart_sifive *regs, const char c)
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{
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if (readl(®s->txfifo) & UART_TXFIFO_FULL)
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return -EAGAIN;
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writel(c, ®s->txfifo);
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return 0;
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}
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static int _sifive_serial_getc(struct uart_sifive *regs)
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{
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int ch = readl(®s->rxfifo);
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if (ch & UART_RXFIFO_EMPTY)
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return -EAGAIN;
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ch &= UART_RXFIFO_DATA;
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return ch;
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}
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static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
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{
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int ret;
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struct clk clk;
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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u32 clock = 0;
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ret = clk_get_by_index(dev, 0, &clk);
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if (IS_ERR_VALUE(ret)) {
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debug("SiFive UART failed to get clock\n");
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ret = dev_read_u32(dev, "clock-frequency", &clock);
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if (IS_ERR_VALUE(ret)) {
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debug("SiFive UART clock not defined\n");
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return 0;
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}
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} else {
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clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(clock)) {
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debug("SiFive UART clock get rate failed\n");
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return 0;
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}
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}
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plat->clock = clock;
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_sifive_serial_setbrg(plat->regs, plat->clock, baudrate);
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return 0;
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}
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static int sifive_serial_probe(struct udevice *dev)
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{
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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/* No need to reinitialize the UART after relocation */
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if (gd->flags & GD_FLG_RELOC)
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return 0;
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_sifive_serial_init(plat->regs);
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return 0;
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}
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static int sifive_serial_getc(struct udevice *dev)
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{
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int c;
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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struct uart_sifive *regs = plat->regs;
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while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
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return c;
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}
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static int sifive_serial_putc(struct udevice *dev, const char ch)
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{
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int rc;
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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while ((rc = _sifive_serial_putc(plat->regs, ch)) == -EAGAIN) ;
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return rc;
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}
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static int sifive_serial_pending(struct udevice *dev, bool input)
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{
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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struct uart_sifive *regs = plat->regs;
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if (input)
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return (readl(®s->ip) & UART_IP_RXWM);
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else
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return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
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}
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static int sifive_serial_of_to_plat(struct udevice *dev)
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{
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struct sifive_uart_plat *plat = dev_get_plat(dev);
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plat->regs = (struct uart_sifive *)(uintptr_t)dev_read_addr(dev);
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if (IS_ERR(plat->regs))
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return PTR_ERR(plat->regs);
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return 0;
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}
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static const struct dm_serial_ops sifive_serial_ops = {
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.putc = sifive_serial_putc,
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.getc = sifive_serial_getc,
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.pending = sifive_serial_pending,
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.setbrg = sifive_serial_setbrg,
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};
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static const struct udevice_id sifive_serial_ids[] = {
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{ .compatible = "sifive,uart0" },
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{ }
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};
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U_BOOT_DRIVER(serial_sifive) = {
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.name = "serial_sifive",
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.id = UCLASS_SERIAL,
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.of_match = sifive_serial_ids,
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.of_to_plat = sifive_serial_of_to_plat,
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.plat_auto = sizeof(struct sifive_uart_plat),
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.probe = sifive_serial_probe,
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.ops = &sifive_serial_ops,
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};
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#ifdef CONFIG_DEBUG_UART_SIFIVE
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static inline void _debug_uart_init(void)
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{
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struct uart_sifive *regs =
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(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
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_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
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CONFIG_BAUDRATE);
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_sifive_serial_init(regs);
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct uart_sifive *regs =
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(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
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while (_sifive_serial_putc(regs, ch) == -EAGAIN)
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schedule();
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}
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DEBUG_UART_FUNCS
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#endif
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