mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 11:00:15 +00:00
29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
430 lines
9.1 KiB
C
430 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* (C) Copyright 2004
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* ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*/
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/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
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#include <common.h>
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#include <asm/global_data.h>
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/* For get_bus_freq() */
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#include <clock_legacy.h>
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#include <dm.h>
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#include <clk.h>
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#include <errno.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <serial.h>
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#include <dm/device_compat.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <linux/compiler.h>
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#include "serial_pl01x_internal.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_DM_SERIAL
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static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
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static enum pl01x_type pl01x_type __section(".data");
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static struct pl01x_regs *base_regs __section(".data");
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#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
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#endif
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static int pl01x_putc(struct pl01x_regs *regs, char c)
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{
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/* Wait until there is space in the FIFO */
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if (readl(®s->fr) & UART_PL01x_FR_TXFF)
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return -EAGAIN;
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/* Send the character */
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writel(c, ®s->dr);
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return 0;
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}
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static int pl01x_getc(struct pl01x_regs *regs)
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{
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unsigned int data;
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/* Wait until there is data in the FIFO */
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if (readl(®s->fr) & UART_PL01x_FR_RXFE)
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return -EAGAIN;
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data = readl(®s->dr);
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/* Check for an error flag */
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if (data & 0xFFFFFF00) {
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/* Clear the error */
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writel(0xFFFFFFFF, ®s->ecr);
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return -1;
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}
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return (int) data;
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}
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static int pl01x_tstc(struct pl01x_regs *regs)
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{
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schedule();
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return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
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}
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static int pl01x_generic_serial_init(struct pl01x_regs *regs,
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enum pl01x_type type)
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{
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switch (type) {
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case TYPE_PL010:
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/* disable everything */
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writel(0, ®s->pl010_cr);
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break;
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case TYPE_PL011:
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/* disable everything */
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writel(0, ®s->pl011_cr);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int pl011_set_line_control(struct pl01x_regs *regs)
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{
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unsigned int lcr;
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/*
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* Internal update of baud rate register require line
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* control register write
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*/
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lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
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writel(lcr, ®s->pl011_lcrh);
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return 0;
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}
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static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
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int clock, int baudrate)
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{
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switch (type) {
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case TYPE_PL010: {
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unsigned int divisor;
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/* disable everything */
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writel(0, ®s->pl010_cr);
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switch (baudrate) {
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case 9600:
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divisor = UART_PL010_BAUD_9600;
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break;
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case 19200:
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divisor = UART_PL010_BAUD_19200;
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break;
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case 38400:
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divisor = UART_PL010_BAUD_38400;
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break;
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case 57600:
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divisor = UART_PL010_BAUD_57600;
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break;
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case 115200:
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divisor = UART_PL010_BAUD_115200;
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break;
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default:
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divisor = UART_PL010_BAUD_38400;
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}
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writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
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writel(divisor & 0xff, ®s->pl010_lcrl);
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/*
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* Set line control for the PL010 to be 8 bits, 1 stop bit,
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* no parity, fifo enabled
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*/
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writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
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®s->pl010_lcrh);
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/* Finally, enable the UART */
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writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
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break;
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}
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case TYPE_PL011: {
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unsigned int temp;
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unsigned int divider;
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unsigned int remainder;
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unsigned int fraction;
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/* Without a valid clock rate we cannot set up the baudrate. */
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if (clock) {
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/*
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* Set baud rate
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*
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* IBRD = UART_CLK / (16 * BAUD_RATE)
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* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
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* / (16 * BAUD_RATE))
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*/
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temp = 16 * baudrate;
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divider = clock / temp;
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remainder = clock % temp;
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temp = (8 * remainder) / baudrate;
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fraction = (temp >> 1) + (temp & 1);
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writel(divider, ®s->pl011_ibrd);
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writel(fraction, ®s->pl011_fbrd);
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}
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pl011_set_line_control(regs);
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/* Finally, enable the UART */
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writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
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UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
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break;
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}
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default:
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return -EINVAL;
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}
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return 0;
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}
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#ifndef CONFIG_DM_SERIAL
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static void pl01x_serial_init_baud(int baudrate)
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{
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int clock = 0;
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#if defined(CONFIG_PL011_SERIAL)
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pl01x_type = TYPE_PL011;
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clock = CONFIG_PL011_CLOCK;
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#endif
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base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
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pl01x_generic_serial_init(base_regs, pl01x_type);
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pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
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}
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/*
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* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
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* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
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* Versatile PB has four UARTs.
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*/
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int pl01x_serial_init(void)
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{
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pl01x_serial_init_baud(CONFIG_BAUDRATE);
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return 0;
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}
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static void pl01x_serial_putc(const char c)
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{
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if (c == '\n')
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while (pl01x_putc(base_regs, '\r') == -EAGAIN);
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while (pl01x_putc(base_regs, c) == -EAGAIN);
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}
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static int pl01x_serial_getc(void)
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{
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while (1) {
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int ch = pl01x_getc(base_regs);
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if (ch == -EAGAIN) {
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schedule();
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continue;
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}
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return ch;
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}
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}
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static int pl01x_serial_tstc(void)
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{
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return pl01x_tstc(base_regs);
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}
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static void pl01x_serial_setbrg(void)
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{
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/*
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* Flush FIFO and wait for non-busy before changing baudrate to avoid
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* crap in console
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*/
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while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
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schedule();
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while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
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schedule();
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pl01x_serial_init_baud(gd->baudrate);
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}
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static struct serial_device pl01x_serial_drv = {
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.name = "pl01x_serial",
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.start = pl01x_serial_init,
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.stop = NULL,
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.setbrg = pl01x_serial_setbrg,
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.putc = pl01x_serial_putc,
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.puts = default_serial_puts,
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.getc = pl01x_serial_getc,
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.tstc = pl01x_serial_tstc,
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};
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void pl01x_serial_initialize(void)
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{
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serial_register(&pl01x_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &pl01x_serial_drv;
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}
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#endif /* nCONFIG_DM_SERIAL */
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#ifdef CONFIG_DM_SERIAL
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int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct pl01x_serial_plat *plat = dev_get_plat(dev);
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struct pl01x_priv *priv = dev_get_priv(dev);
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if (!plat->skip_init) {
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pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
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baudrate);
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}
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return 0;
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}
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int pl01x_serial_probe(struct udevice *dev)
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{
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struct pl01x_serial_plat *plat = dev_get_plat(dev);
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struct pl01x_priv *priv = dev_get_priv(dev);
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priv->regs = (struct pl01x_regs *)plat->base;
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priv->type = plat->type;
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if (!plat->skip_init)
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return pl01x_generic_serial_init(priv->regs, priv->type);
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else
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return 0;
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}
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int pl01x_serial_getc(struct udevice *dev)
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{
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struct pl01x_priv *priv = dev_get_priv(dev);
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return pl01x_getc(priv->regs);
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}
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int pl01x_serial_putc(struct udevice *dev, const char ch)
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{
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struct pl01x_priv *priv = dev_get_priv(dev);
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return pl01x_putc(priv->regs, ch);
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}
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int pl01x_serial_pending(struct udevice *dev, bool input)
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{
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struct pl01x_priv *priv = dev_get_priv(dev);
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unsigned int fr = readl(&priv->regs->fr);
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if (input)
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return pl01x_tstc(priv->regs);
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else
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return fr & UART_PL01x_FR_TXFF ? 0 : 1;
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}
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static const struct dm_serial_ops pl01x_serial_ops = {
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.putc = pl01x_serial_putc,
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.pending = pl01x_serial_pending,
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.getc = pl01x_serial_getc,
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.setbrg = pl01x_serial_setbrg,
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};
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#if CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct udevice_id pl01x_serial_id[] ={
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{.compatible = "arm,pl011", .data = TYPE_PL011},
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{.compatible = "arm,pl010", .data = TYPE_PL010},
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{}
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};
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#ifndef CONFIG_PL011_CLOCK
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#define CONFIG_PL011_CLOCK 0
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#endif
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int pl01x_serial_of_to_plat(struct udevice *dev)
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{
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struct pl01x_serial_plat *plat = dev_get_plat(dev);
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struct clk clk;
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fdt_addr_t addr;
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int ret;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = addr;
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plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
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ret = clk_get_by_index(dev, 0, &clk);
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if (!ret) {
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ret = clk_enable(&clk);
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if (ret && ret != -ENOSYS) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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plat->clock = clk_get_rate(&clk);
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if (IS_ERR_VALUE(plat->clock)) {
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dev_err(dev, "failed to get rate\n");
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return plat->clock;
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}
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debug("%s: CLK %d\n", __func__, plat->clock);
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}
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plat->type = dev_get_driver_data(dev);
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plat->skip_init = dev_read_bool(dev, "skip-init");
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return 0;
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}
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#endif
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U_BOOT_DRIVER(serial_pl01x) = {
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.name = "serial_pl01x",
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.id = UCLASS_SERIAL,
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.of_match = of_match_ptr(pl01x_serial_id),
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.of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
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.plat_auto = sizeof(struct pl01x_serial_plat),
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.probe = pl01x_serial_probe,
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.ops = &pl01x_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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.priv_auto = sizeof(struct pl01x_priv),
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};
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#endif
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#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
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#include <debug_uart.h>
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static void _debug_uart_init(void)
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{
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#ifndef CONFIG_DEBUG_UART_SKIP_INIT
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struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
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enum pl01x_type type;
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if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
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type = TYPE_PL011;
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else
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type = TYPE_PL010;
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pl01x_generic_serial_init(regs, type);
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pl01x_generic_setbrg(regs, type,
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CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
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#endif
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
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while (pl01x_putc(regs, ch) == -EAGAIN)
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;
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}
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DEBUG_UART_FUNCS
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#endif
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