mirror of
https://github.com/AsahiLinux/u-boot
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6f6a0b74d6
Add Nuvoton BMC NPCM7xx/NPCM8xx uart driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <serial.h>
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struct npcm_uart {
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union {
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u32 rbr; /* Receive Buffer Register */
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u32 thr; /* Transmit Holding Register */
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u32 dll; /* Divisor Latch (Low Byte) Register */
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};
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union {
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u32 ier; /* Interrupt Enable Register */
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u32 dlm; /* Divisor Latch (Low Byte) Register */
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};
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union {
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u32 iir; /* Interrupt Identification Register */
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u32 fcr; /* FIFO Control Register */
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};
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u32 lcr; /* Line Control Register */
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u32 mcr; /* Modem Control Register */
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u32 lsr; /* Line Status Control Register */
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u32 msr; /* Modem Status Register */
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u32 tor; /* Timeout Register */
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};
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#define LCR_WLS_8BITS 3 /* 8-bit word length select */
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#define FCR_TFR BIT(2) /* TxFIFO reset */
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#define FCR_RFR BIT(1) /* RxFIFO reset */
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#define FCR_FME BIT(0) /* FIFO mode enable */
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#define LSR_THRE BIT(5) /* Status of TxFIFO empty */
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#define LSR_RFDR BIT(0) /* Status of RxFIFO data ready */
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#define LCR_DLAB BIT(7) /* Divisor latch access bit */
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struct npcm_serial_plat {
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struct npcm_uart *reg;
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u32 uart_clk; /* frequency of uart clock source */
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};
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static int npcm_serial_pending(struct udevice *dev, bool input)
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{
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struct npcm_serial_plat *plat = dev_get_plat(dev);
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struct npcm_uart *uart = plat->reg;
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if (input)
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return readb(&uart->lsr) & LSR_RFDR ? 1 : 0;
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else
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return readb(&uart->lsr) & LSR_THRE ? 0 : 1;
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}
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static int npcm_serial_putc(struct udevice *dev, const char ch)
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{
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struct npcm_serial_plat *plat = dev_get_plat(dev);
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struct npcm_uart *uart = plat->reg;
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if (!(readb(&uart->lsr) & LSR_THRE))
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return -EAGAIN;
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writeb(ch, &uart->thr);
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return 0;
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}
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static int npcm_serial_getc(struct udevice *dev)
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{
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struct npcm_serial_plat *plat = dev_get_plat(dev);
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struct npcm_uart *uart = plat->reg;
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if (!(readb(&uart->lsr) & LSR_RFDR))
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return -EAGAIN;
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return readb(&uart->rbr);
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}
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static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct npcm_serial_plat *plat = dev_get_plat(dev);
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struct npcm_uart *uart = plat->reg;
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u16 divisor;
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/* BaudOut = UART Clock / (16 * [Divisor + 2]) */
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divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
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setbits_8(&uart->lcr, LCR_DLAB);
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writeb(divisor & 0xff, &uart->dll);
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writeb(divisor >> 8, &uart->dlm);
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clrbits_8(&uart->lcr, LCR_DLAB);
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return 0;
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}
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static int npcm_serial_probe(struct udevice *dev)
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{
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struct npcm_serial_plat *plat = dev_get_plat(dev);
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struct npcm_uart *uart = plat->reg;
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struct clk clk, parent;
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u32 freq;
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int ret;
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plat->reg = dev_read_addr_ptr(dev);
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freq = dev_read_u32_default(dev, "clock-frequency", 0);
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_index(dev, 1, &parent);
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if (!ret) {
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ret = clk_set_parent(&clk, &parent);
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if (ret)
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return ret;
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}
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ret = clk_set_rate(&clk, freq);
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if (ret < 0)
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return ret;
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plat->uart_clk = ret;
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/* Disable all interrupt */
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writeb(0, &uart->ier);
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/* Set 8 bit, 1 stop, no parity */
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writeb(LCR_WLS_8BITS, &uart->lcr);
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/* Reset RX/TX FIFO */
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writeb(FCR_FME | FCR_RFR | FCR_TFR, &uart->fcr);
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return 0;
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}
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static const struct dm_serial_ops npcm_serial_ops = {
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.getc = npcm_serial_getc,
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.setbrg = npcm_serial_setbrg,
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.putc = npcm_serial_putc,
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.pending = npcm_serial_pending,
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};
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static const struct udevice_id npcm_serial_ids[] = {
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{ .compatible = "nuvoton,npcm750-uart" },
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{ .compatible = "nuvoton,npcm845-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_npcm) = {
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.name = "serial_npcm",
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.id = UCLASS_SERIAL,
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.of_match = npcm_serial_ids,
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.plat_auto = sizeof(struct npcm_serial_plat),
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.probe = npcm_serial_probe,
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.ops = &npcm_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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