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9b075973e9
Add support for the PWM found on the SAMA5D2 family of devices. Signed-off-by: Dan Sneddon <dan.sneddon@microchip.com>
207 lines
4.7 KiB
C
207 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PWM support for Microchip AT91 architectures.
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*
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* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Dan Sneddon <daniel.sneddon@microchip.com>
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*
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* Based on drivers/pwm/pwm-atmel.c from Linux.
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*/
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#include <clk.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <pwm.h>
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#define PERIOD_BITS 16
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#define PWM_MAX_PRES 10
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#define NSEC_PER_SEC 1000000000L
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#define PWM_ENA 0x04
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#define PWM_CHANNEL_OFFSET 0x20
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#define PWM_CMR 0x200
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#define PWM_CMR_CPRE_MSK GENMASK(3, 0)
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#define PWM_CMR_CPOL BIT(9)
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#define PWM_CDTY 0x204
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#define PWM_CPRD 0x20C
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struct at91_pwm_priv {
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void __iomem *base;
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struct clk pclk;
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u32 clkrate;
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};
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static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev,
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unsigned long clkrate,
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uint period_ns, uint duty_ns,
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unsigned long *cprd, u32 *pres)
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{
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u64 cycles = period_ns;
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int shift;
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/* Calculate the period cycles and prescale value */
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cycles *= clkrate;
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do_div(cycles, NSEC_PER_SEC);
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/*
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* The register for the period length is period_bits bits wide.
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* So for each bit the number of clock cycles is wider divide the input
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* clock frequency by two using pres and shift cprd accordingly.
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*/
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shift = fls(cycles) - PERIOD_BITS;
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if (shift > PWM_MAX_PRES) {
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return -EINVAL;
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} else if (shift > 0) {
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*pres = shift;
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cycles >>= *pres;
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} else {
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*pres = 0;
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}
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*cprd = cycles;
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return 0;
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}
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static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns,
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unsigned long clkrate, unsigned long cprd,
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u32 pres, unsigned long *cdty)
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{
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u64 cycles = duty_ns;
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cycles *= clkrate;
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do_div(cycles, NSEC_PER_SEC);
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cycles >>= pres;
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*cdty = cprd - cycles;
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}
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/**
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* Returns: channel status after set operation
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*/
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static bool at91_pwm_set(void __iomem *base, uint channel, bool enable)
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{
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u32 val, cur_status;
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val = ioread32(base + PWM_ENA);
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cur_status = !!(val & BIT(channel));
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/* if channel is already in that state, do nothing */
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if (!(enable ^ cur_status))
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return cur_status;
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if (enable)
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val |= BIT(channel);
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else
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val &= ~(BIT(channel));
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iowrite32(val, base + PWM_ENA);
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return cur_status;
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}
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static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct at91_pwm_priv *priv = dev_get_priv(dev);
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at91_pwm_set(priv->base, channel, enable);
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return 0;
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}
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static int at91_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct at91_pwm_priv *priv = dev_get_priv(dev);
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unsigned long cprd, cdty;
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u32 pres, val;
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int channel_enabled;
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int ret;
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ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns,
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duty_ns, &cprd, &pres);
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if (ret)
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return ret;
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at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty);
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/* disable the channel */
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channel_enabled = at91_pwm_set(priv->base, channel, false);
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/* It is necessary to preserve CPOL, inside CMR */
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val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
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val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
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iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
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iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD);
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iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY);
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/* renable the channel if needed */
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if (channel_enabled)
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at91_pwm_set(priv->base, channel, true);
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return 0;
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}
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static int at91_pwm_set_invert(struct udevice *dev, uint channel,
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bool polarity)
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{
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struct at91_pwm_priv *priv = dev_get_priv(dev);
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u32 val;
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val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
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if (polarity)
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val |= PWM_CMR_CPOL;
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else
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val &= ~PWM_CMR_CPOL;
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iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR);
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return 0;
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}
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static int at91_pwm_probe(struct udevice *dev)
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{
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struct at91_pwm_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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ret = clk_get_by_index(dev, 0, &priv->pclk);
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if (ret)
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return ret;
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/* clocks aren't ref-counted so just enabled them once here */
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ret = clk_enable(&priv->pclk);
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if (ret)
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return ret;
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priv->clkrate = clk_get_rate(&priv->pclk);
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return ret;
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}
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static const struct pwm_ops at91_pwm_ops = {
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.set_config = at91_pwm_set_config,
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.set_enable = at91_pwm_set_enable,
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.set_invert = at91_pwm_set_invert,
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};
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static const struct udevice_id at91_pwm_of_match[] = {
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{ .compatible = "atmel,sama5d2-pwm" },
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{ }
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};
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U_BOOT_DRIVER(at91_pwm) = {
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.name = "at91_pwm",
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.id = UCLASS_PWM,
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.of_match = at91_pwm_of_match,
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.probe = at91_pwm_probe,
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.priv_auto = sizeof(struct at91_pwm_priv),
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.ops = &at91_pwm_ops,
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};
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