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fae101d6e8
This patch add the support of PWM controller which can be found at aspeed ast2600 soc. The pwm supoorts up to 16 channels and it's part function of multi-function device "pwm-tach controller". Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
251 lines
7.5 KiB
C
251 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Aspeed Technology Inc.
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*
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* PWM controller driver for Aspeed ast2600 SoCs.
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* This drivers doesn't support earlier version of the IP.
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*
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* The formula of pwm period duration:
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* period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
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*
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* The formula of pwm duty cycle duration:
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* duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
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* = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
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*
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* The software driver fixes the period to 255, which causes the high-frequency
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* precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
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*
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* Register usage:
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* PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
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* Use to determine whether the PWM channel is enabled or disabled
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* CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
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* output low to the PIN_ENABLE mux after that the driver can still change the pwm period
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* and duty and the value will apply when CLK_ENABLE be set again.
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* Use to determine whether duty_cycle bigger than 0.
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* PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
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* PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
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* values are equal it means the duty cycle = 100%.
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*
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* Limitations:
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* - When changing both duty cycle and period, we cannot prevent in
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* software that the output might produce a period with mixed
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* settings.
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* - Disabling the PWM doesn't complete the current period.
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*
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* Improvements:
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* - When only changing one of duty cycle or period, our pwm controller will not
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* generate the glitch, the configure will change at next cycle of pwm.
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* This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
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*/
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <pwm.h>
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#include <clk.h>
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#include <reset.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dm/device_compat.h>
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#include <linux/math64.h>
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#include <linux/bitfield.h>
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#include <asm/io.h>
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/* The channel number of Aspeed pwm controller */
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#define PWM_ASPEED_NR_PWMS 16
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/* PWM Control Register */
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#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
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#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
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#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
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#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
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#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
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#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
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#define PWM_ASPEED_CTRL_INVERSE BIT(14)
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#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
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#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
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#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
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#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
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/* PWM Duty Cycle Register */
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#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
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#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
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#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
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#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
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#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
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/* PWM fixed value */
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#define PWM_ASPEED_FIXED_PERIOD 0xff
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#define NSEC_PER_SEC 1000000000L
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struct aspeed_pwm_priv {
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struct clk clk;
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struct regmap *regmap;
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struct reset_ctl reset;
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};
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static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
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{
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struct aspeed_pwm_priv *priv = dev_get_priv(dev);
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if (channel >= PWM_ASPEED_NR_PWMS)
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return -EINVAL;
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regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
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PWM_ASPEED_CTRL_INVERSE,
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FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
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polarity));
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return 0;
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}
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static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct aspeed_pwm_priv *priv = dev_get_priv(dev);
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if (channel >= PWM_ASPEED_NR_PWMS)
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return -EINVAL;
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regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
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PWM_ASPEED_CTRL_PIN_ENABLE,
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enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
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return 0;
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}
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static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct aspeed_pwm_priv *priv = dev_get_priv(dev);
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u32 duty_pt;
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unsigned long rate;
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u64 div_h, div_l, divisor;
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bool clk_en;
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if (channel >= PWM_ASPEED_NR_PWMS)
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return -EINVAL;
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dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
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duty_ns);
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rate = clk_get_rate(&priv->clk);
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/*
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* Pick the smallest value for div_h so that div_l can be the biggest
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* which results in a finer resolution near the target period value.
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*/
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divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
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(PWM_ASPEED_CTRL_CLK_DIV_L + 1);
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div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
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if (div_h > 0xf)
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div_h = 0xf;
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divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
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div_l = div64_u64((u64)rate * period_ns, divisor);
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if (div_l == 0)
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return -ERANGE;
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div_l -= 1;
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if (div_l > 255)
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div_l = 255;
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dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
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div_l);
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/* duty_pt = duty_cycle * (PERIOD + 1) / period */
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duty_pt = div64_u64(duty_ns * (u64)rate,
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(u64)NSEC_PER_SEC * (div_l + 1) << div_h);
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dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
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duty_pt);
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if (duty_pt == 0) {
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clk_en = 0;
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} else {
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clk_en = 1;
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if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
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duty_pt = 0;
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/*
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* Fixed DUTY_CYCLE_PERIOD to its max value to get a
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* fine-grained resolution for duty_cycle at the expense of a
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* coarser period resolution.
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*/
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regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
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PWM_ASPEED_DUTY_CYCLE_PERIOD |
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PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
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PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
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FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
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PWM_ASPEED_FIXED_PERIOD) |
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FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
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duty_pt));
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}
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regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
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PWM_ASPEED_CTRL_CLK_DIV_H |
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PWM_ASPEED_CTRL_CLK_DIV_L |
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PWM_ASPEED_CTRL_CLK_ENABLE,
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FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
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FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
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FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
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return 0;
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}
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static int aspeed_pwm_probe(struct udevice *dev)
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{
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int ret;
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struct aspeed_pwm_priv *priv = dev_get_priv(dev);
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struct udevice *parent_dev = dev_get_parent(dev);
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priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
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if (IS_ERR(priv->regmap)) {
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dev_err(dev, "Couldn't get regmap\n");
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return PTR_ERR(priv->regmap);
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}
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ret = clk_get_by_index(parent_dev, 0, &priv->clk);
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if (ret < 0) {
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dev_err(dev, "get clock failed\n");
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return ret;
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}
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ret = reset_get_by_index(parent_dev, 0, &priv->reset);
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if (ret) {
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dev_err(dev, "get reset failed\n");
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return ret;
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}
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ret = reset_deassert(&priv->reset);
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if (ret) {
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dev_err(dev, "cannot deassert reset control: %pe\n",
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ERR_PTR(ret));
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return ret;
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}
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return 0;
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}
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static int aspeed_pwm_remove(struct udevice *dev)
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{
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struct aspeed_pwm_priv *priv = dev_get_priv(dev);
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reset_assert(&priv->reset);
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return 0;
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}
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static const struct pwm_ops aspeed_pwm_ops = {
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.set_invert = aspeed_pwm_set_invert,
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.set_config = aspeed_pwm_set_config,
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.set_enable = aspeed_pwm_set_enable,
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};
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static const struct udevice_id aspeed_pwm_ids[] = {
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{ .compatible = "aspeed,ast2600-pwm" },
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{ }
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};
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U_BOOT_DRIVER(aspeed_pwm) = {
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.name = "aspeed_pwm",
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.id = UCLASS_PWM,
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.of_match = aspeed_pwm_ids,
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.ops = &aspeed_pwm_ops,
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.probe = aspeed_pwm_probe,
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.remove = aspeed_pwm_remove,
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.priv_auto = sizeof(struct aspeed_pwm_priv),
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};
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