mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
969 lines
25 KiB
C
969 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale Three Speed Ethernet Controller driver
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*
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* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* author Andy Fleming
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#include <tsec.h>
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#include <fsl_mdio.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <miiphy.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#ifndef CONFIG_DM_ETH
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/* Default initializations for TSEC controllers. */
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static struct tsec_info_struct tsec_info[] = {
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#ifdef CONFIG_TSEC1
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STD_TSEC_INFO(1), /* TSEC1 */
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#endif
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#ifdef CONFIG_TSEC2
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STD_TSEC_INFO(2), /* TSEC2 */
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#endif
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#ifdef CONFIG_MPC85XX_FEC
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{
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.regs = TSEC_GET_REGS(2, 0x2000),
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.devname = CONFIG_MPC85XX_FEC_NAME,
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.phyaddr = FEC_PHY_ADDR,
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.flags = FEC_FLAGS,
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.mii_devname = DEFAULT_MII_NAME
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}, /* FEC */
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#endif
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#ifdef CONFIG_TSEC3
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STD_TSEC_INFO(3), /* TSEC3 */
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#endif
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#ifdef CONFIG_TSEC4
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STD_TSEC_INFO(4), /* TSEC4 */
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#endif
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};
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#endif /* CONFIG_DM_ETH */
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#define TBIANA_SETTINGS ( \
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TBIANA_ASYMMETRIC_PAUSE \
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| TBIANA_SYMMETRIC_PAUSE \
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| TBIANA_FULL_DUPLEX \
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)
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/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
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#ifndef CONFIG_TSEC_TBICR_SETTINGS
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#define CONFIG_TSEC_TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_ANEG_ENABLE \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
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#endif /* CONFIG_TSEC_TBICR_SETTINGS */
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/* Configure the TBI for SGMII operation */
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static void tsec_configure_serdes(struct tsec_private *priv)
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{
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/*
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* Access TBI PHY registers at given TSEC register offset as opposed
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* to the register offset used for external PHY accesses
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*/
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_ANA, TBIANA_SETTINGS);
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_TBICON, TBICON_CLK_SELECT);
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
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0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
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}
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/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
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* and this is the ethernet-crc method needed for TSEC -- and perhaps
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* some other adapter -- hash tables
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*/
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#define CRCPOLY_LE 0xedb88320
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static u32 ether_crc(size_t len, unsigned char const *p)
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{
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int i;
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u32 crc;
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crc = ~0;
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while (len--) {
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crc ^= *p++;
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for (i = 0; i < 8; i++)
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crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
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}
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/* an reverse the bits, cuz of way they arrive -- last-first */
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crc = (crc >> 16) | (crc << 16);
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crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
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crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
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crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
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crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
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return crc;
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}
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/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
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/* Set the appropriate hash bit for the given addr */
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/*
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* The algorithm works like so:
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* 1) Take the Destination Address (ie the multicast address), and
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* do a CRC on it (little endian), and reverse the bits of the
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* result.
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* 2) Use the 8 most significant bits as a hash into a 256-entry
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* table. The table is controlled through 8 32-bit registers:
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* gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
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* 255. This means that the 3 most significant bits in the
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* hash index which gaddr register to use, and the 5 other bits
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* indicate which bit (assuming an IBM numbering scheme, which
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* for PowerPC (tm) is usually the case) in the register holds
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* the entry.
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*/
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#ifndef CONFIG_DM_ETH
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static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
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int join)
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#else
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static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
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#endif
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{
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struct tsec_private *priv;
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struct tsec __iomem *regs;
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u32 result, value;
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u8 whichbit, whichreg;
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#ifndef CONFIG_DM_ETH
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priv = (struct tsec_private *)dev->priv;
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#else
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priv = dev_get_priv(dev);
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#endif
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regs = priv->regs;
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result = ether_crc(MAC_ADDR_LEN, mcast_mac);
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whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
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whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
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value = BIT(31 - whichbit);
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if (join)
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setbits_be32(®s->hash.gaddr0 + whichreg, value);
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else
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clrbits_be32(®s->hash.gaddr0 + whichreg, value);
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return 0;
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}
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static int __maybe_unused tsec_set_promisc(struct udevice *dev, bool enable)
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{
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struct tsec_private *priv = dev_get_priv(dev);
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struct tsec __iomem *regs = priv->regs;
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if (enable)
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setbits_be32(®s->rctrl, RCTRL_PROM);
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else
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clrbits_be32(®s->rctrl, RCTRL_PROM);
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return 0;
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}
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/*
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* Initialized required registers to appropriate values, zeroing
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* those we don't care about (unless zero is bad, in which case,
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* choose a more appropriate value)
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*/
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static void init_registers(struct tsec __iomem *regs)
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{
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/* Clear IEVENT */
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out_be32(®s->ievent, IEVENT_INIT_CLEAR);
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out_be32(®s->imask, IMASK_INIT_CLEAR);
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out_be32(®s->hash.iaddr0, 0);
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out_be32(®s->hash.iaddr1, 0);
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out_be32(®s->hash.iaddr2, 0);
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out_be32(®s->hash.iaddr3, 0);
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out_be32(®s->hash.iaddr4, 0);
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out_be32(®s->hash.iaddr5, 0);
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out_be32(®s->hash.iaddr6, 0);
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out_be32(®s->hash.iaddr7, 0);
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out_be32(®s->hash.gaddr0, 0);
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out_be32(®s->hash.gaddr1, 0);
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out_be32(®s->hash.gaddr2, 0);
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out_be32(®s->hash.gaddr3, 0);
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out_be32(®s->hash.gaddr4, 0);
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out_be32(®s->hash.gaddr5, 0);
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out_be32(®s->hash.gaddr6, 0);
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out_be32(®s->hash.gaddr7, 0);
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/* Init RMON mib registers */
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memset((void *)®s->rmon, 0, sizeof(regs->rmon));
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out_be32(®s->rmon.cam1, 0xffffffff);
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out_be32(®s->rmon.cam2, 0xffffffff);
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out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
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out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
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out_be32(®s->attr, ATTR_INIT_SETTINGS);
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out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
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}
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/*
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* Configure maccfg2 based on negotiated speed and duplex
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* reported by PHY handling code
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*/
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static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
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{
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struct tsec __iomem *regs = priv->regs;
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u32 ecntrl, maccfg2;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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/* clear all bits relative with interface mode */
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ecntrl = in_be32(®s->ecntrl);
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ecntrl &= ~ECNTRL_R100;
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maccfg2 = in_be32(®s->maccfg2);
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maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
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if (phydev->duplex)
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maccfg2 |= MACCFG2_FULL_DUPLEX;
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switch (phydev->speed) {
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case 1000:
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maccfg2 |= MACCFG2_GMII;
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break;
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case 100:
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case 10:
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maccfg2 |= MACCFG2_MII;
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/*
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* Set R100 bit in all modes although
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* it is only used in RGMII mode
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*/
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if (phydev->speed == 100)
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ecntrl |= ECNTRL_R100;
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break;
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default:
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printf("%s: Speed was bad\n", phydev->dev->name);
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break;
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}
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out_be32(®s->ecntrl, ecntrl);
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out_be32(®s->maccfg2, maccfg2);
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printf("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
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/*
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* This returns the status bits of the device. The return value
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* is never checked, and this is what the 8260 driver did, so we
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* do the same. Presumably, this would be zero if there were no
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* errors
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*/
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#ifndef CONFIG_DM_ETH
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static int tsec_send(struct eth_device *dev, void *packet, int length)
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#else
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static int tsec_send(struct udevice *dev, void *packet, int length)
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#endif
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{
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struct tsec_private *priv;
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struct tsec __iomem *regs;
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int result = 0;
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u16 status;
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int i;
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#ifndef CONFIG_DM_ETH
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priv = (struct tsec_private *)dev->priv;
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#else
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priv = dev_get_priv(dev);
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#endif
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regs = priv->regs;
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/* Find an empty buffer descriptor */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tsec: tx buffers full\n", dev->name);
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return result;
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}
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}
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out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
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out_be16(&priv->txbd[priv->tx_idx].length, length);
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status = in_be16(&priv->txbd[priv->tx_idx].status);
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out_be16(&priv->txbd[priv->tx_idx].status, status |
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
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/* Tell the DMA to go */
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out_be32(®s->tstat, TSTAT_CLEAR_THALT);
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/* Wait for buffer to be transmitted */
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for (i = 0;
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
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i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tsec: tx error\n", dev->name);
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return result;
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}
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}
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priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
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result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
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return result;
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}
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#ifndef CONFIG_DM_ETH
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static int tsec_recv(struct eth_device *dev)
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{
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struct tsec_private *priv = (struct tsec_private *)dev->priv;
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struct tsec __iomem *regs = priv->regs;
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while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
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int length = in_be16(&priv->rxbd[priv->rx_idx].length);
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u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
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uchar *packet = net_rx_packets[priv->rx_idx];
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/* Send the packet up if there were no errors */
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if (!(status & RXBD_STATS))
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net_process_received_packet(packet, length - 4);
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else
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printf("Got error %x\n", (status & RXBD_STATS));
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out_be16(&priv->rxbd[priv->rx_idx].length, 0);
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status = RXBD_EMPTY;
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/* Set the wrap bit if this is the last element in the list */
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if ((priv->rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&priv->rxbd[priv->rx_idx].status, status);
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
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}
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if (in_be32(®s->ievent) & IEVENT_BSY) {
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out_be32(®s->ievent, IEVENT_BSY);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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}
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return -1;
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}
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#else
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static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
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struct tsec __iomem *regs = priv->regs;
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int ret = -1;
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if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
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int length = in_be16(&priv->rxbd[priv->rx_idx].length);
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u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
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u32 buf;
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/* Send the packet up if there were no errors */
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if (!(status & RXBD_STATS)) {
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buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
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*packetp = (uchar *)buf;
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ret = length - 4;
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} else {
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printf("Got error %x\n", (status & RXBD_STATS));
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}
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}
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if (in_be32(®s->ievent) & IEVENT_BSY) {
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out_be32(®s->ievent, IEVENT_BSY);
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
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}
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return ret;
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}
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static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
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u16 status;
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out_be16(&priv->rxbd[priv->rx_idx].length, 0);
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status = RXBD_EMPTY;
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/* Set the wrap bit if this is the last element in the list */
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if ((priv->rx_idx + 1) == PKTBUFSRX)
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status |= RXBD_WRAP;
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out_be16(&priv->rxbd[priv->rx_idx].status, status);
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
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return 0;
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}
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#endif
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/* Stop the interface */
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#ifndef CONFIG_DM_ETH
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static void tsec_halt(struct eth_device *dev)
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#else
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static void tsec_halt(struct udevice *dev)
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#endif
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{
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struct tsec_private *priv;
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struct tsec __iomem *regs;
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#ifndef CONFIG_DM_ETH
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priv = (struct tsec_private *)dev->priv;
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#else
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priv = dev_get_priv(dev);
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#endif
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regs = priv->regs;
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
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while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
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!= (IEVENT_GRSC | IEVENT_GTSC))
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;
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clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
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/* Shut down the PHY, as needed */
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phy_shutdown(priv->phydev);
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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/*
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* When MACCFG1[Rx_EN] is enabled during system boot as part
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* of the eTSEC port initialization sequence,
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* the eTSEC Rx logic may not be properly initialized.
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*/
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static void redundant_init(struct tsec_private *priv)
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{
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struct tsec __iomem *regs = priv->regs;
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uint t, count = 0;
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int fail = 1;
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static const u8 pkt[] = {
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0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
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0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
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0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
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0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
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0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
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0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
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0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
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0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
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0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
|
|
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
|
|
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
|
|
0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
|
|
0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
|
|
0x71, 0x72};
|
|
|
|
/* Enable promiscuous mode */
|
|
setbits_be32(®s->rctrl, RCTRL_PROM);
|
|
/* Enable loopback mode */
|
|
setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
|
|
/* Enable transmit and receive */
|
|
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
|
|
|
|
/* Tell the DMA it is clear to go */
|
|
setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
|
|
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
|
|
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
|
|
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
|
|
|
do {
|
|
u16 status;
|
|
|
|
tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
|
|
|
|
/* Wait for buffer to be received */
|
|
for (t = 0;
|
|
in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
|
|
t++) {
|
|
if (t >= 10 * TOUT_LOOP) {
|
|
printf("%s: tsec: rx error\n", priv->dev->name);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
|
|
fail = 0;
|
|
|
|
out_be16(&priv->rxbd[priv->rx_idx].length, 0);
|
|
status = RXBD_EMPTY;
|
|
if ((priv->rx_idx + 1) == PKTBUFSRX)
|
|
status |= RXBD_WRAP;
|
|
out_be16(&priv->rxbd[priv->rx_idx].status, status);
|
|
priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
|
|
|
|
if (in_be32(®s->ievent) & IEVENT_BSY) {
|
|
out_be32(®s->ievent, IEVENT_BSY);
|
|
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
|
|
}
|
|
if (fail) {
|
|
printf("loopback recv packet error!\n");
|
|
clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
|
|
udelay(1000);
|
|
setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
|
|
}
|
|
} while ((count++ < 4) && (fail == 1));
|
|
|
|
if (fail)
|
|
panic("eTSEC init fail!\n");
|
|
/* Disable promiscuous mode */
|
|
clrbits_be32(®s->rctrl, RCTRL_PROM);
|
|
/* Disable loopback mode */
|
|
clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Set up the buffers and their descriptors, and bring up the
|
|
* interface
|
|
*/
|
|
static void startup_tsec(struct tsec_private *priv)
|
|
{
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u16 status;
|
|
int i;
|
|
|
|
/* reset the indices to zero */
|
|
priv->rx_idx = 0;
|
|
priv->tx_idx = 0;
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
|
|
uint svr;
|
|
#endif
|
|
|
|
/* Point to the buffer descriptors */
|
|
out_be32(®s->tbase, (u32)&priv->txbd[0]);
|
|
out_be32(®s->rbase, (u32)&priv->rxbd[0]);
|
|
|
|
/* Initialize the Rx Buffer descriptors */
|
|
for (i = 0; i < PKTBUFSRX; i++) {
|
|
out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
|
|
out_be16(&priv->rxbd[i].length, 0);
|
|
out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
|
|
}
|
|
status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
|
|
out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
|
|
|
|
/* Initialize the TX Buffer Descriptors */
|
|
for (i = 0; i < TX_BUF_CNT; i++) {
|
|
out_be16(&priv->txbd[i].status, 0);
|
|
out_be16(&priv->txbd[i].length, 0);
|
|
out_be32(&priv->txbd[i].bufptr, 0);
|
|
}
|
|
status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
|
|
out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
|
|
svr = get_svr();
|
|
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
|
|
redundant_init(priv);
|
|
#endif
|
|
/* Enable Transmit and Receive */
|
|
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
|
|
|
|
/* Tell the DMA it is clear to go */
|
|
setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
|
|
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
|
|
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
|
|
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
|
|
}
|
|
|
|
/*
|
|
* Initializes data structures and registers for the controller,
|
|
* and brings the interface up. Returns the link status, meaning
|
|
* that it returns success if the link is up, failure otherwise.
|
|
* This allows U-Boot to find the first active controller.
|
|
*/
|
|
#ifndef CONFIG_DM_ETH
|
|
static int tsec_init(struct eth_device *dev, struct bd_info *bd)
|
|
#else
|
|
static int tsec_init(struct udevice *dev)
|
|
#endif
|
|
{
|
|
struct tsec_private *priv;
|
|
struct tsec __iomem *regs;
|
|
#ifdef CONFIG_DM_ETH
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
#else
|
|
struct eth_device *pdata = dev;
|
|
#endif
|
|
u32 tempval;
|
|
int ret;
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
priv = (struct tsec_private *)dev->priv;
|
|
#else
|
|
priv = dev_get_priv(dev);
|
|
#endif
|
|
regs = priv->regs;
|
|
/* Make sure the controller is stopped */
|
|
tsec_halt(dev);
|
|
|
|
/* Init MACCFG2. Defaults to GMII */
|
|
out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
|
|
|
|
/* Init ECNTRL */
|
|
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
|
|
|
|
/*
|
|
* Copy the station address into the address registers.
|
|
* For a station address of 0x12345678ABCD in transmission
|
|
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
|
|
* MACnADDR2 is set to 0x34120000.
|
|
*/
|
|
tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
|
|
(pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
|
|
|
|
out_be32(®s->macstnaddr1, tempval);
|
|
|
|
tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
|
|
|
|
out_be32(®s->macstnaddr2, tempval);
|
|
|
|
/* Clear out (for the most part) the other registers */
|
|
init_registers(regs);
|
|
|
|
/* Ready the device for tx/rx */
|
|
startup_tsec(priv);
|
|
|
|
/* Start up the PHY */
|
|
ret = phy_startup(priv->phydev);
|
|
if (ret) {
|
|
printf("Could not initialize PHY %s\n",
|
|
priv->phydev->dev->name);
|
|
return ret;
|
|
}
|
|
|
|
adjust_link(priv, priv->phydev);
|
|
|
|
/* If there's no link, fail */
|
|
return priv->phydev->link ? 0 : -1;
|
|
}
|
|
|
|
static phy_interface_t __maybe_unused tsec_get_interface(struct tsec_private *priv)
|
|
{
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u32 ecntrl;
|
|
|
|
ecntrl = in_be32(®s->ecntrl);
|
|
|
|
if (ecntrl & ECNTRL_SGMII_MODE)
|
|
return PHY_INTERFACE_MODE_SGMII;
|
|
|
|
if (ecntrl & ECNTRL_TBI_MODE) {
|
|
if (ecntrl & ECNTRL_REDUCED_MODE)
|
|
return PHY_INTERFACE_MODE_RTBI;
|
|
else
|
|
return PHY_INTERFACE_MODE_TBI;
|
|
}
|
|
|
|
if (ecntrl & ECNTRL_REDUCED_MODE) {
|
|
phy_interface_t interface;
|
|
|
|
if (ecntrl & ECNTRL_REDUCED_MII_MODE)
|
|
return PHY_INTERFACE_MODE_RMII;
|
|
|
|
interface = priv->interface;
|
|
|
|
/*
|
|
* This isn't autodetected, so it must
|
|
* be set by the platform code.
|
|
*/
|
|
if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
|
interface == PHY_INTERFACE_MODE_RGMII_TXID ||
|
|
interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
|
return interface;
|
|
|
|
return PHY_INTERFACE_MODE_RGMII;
|
|
}
|
|
|
|
if (priv->flags & TSEC_GIGABIT)
|
|
return PHY_INTERFACE_MODE_GMII;
|
|
|
|
return PHY_INTERFACE_MODE_MII;
|
|
}
|
|
|
|
/*
|
|
* Discover which PHY is attached to the device, and configure it
|
|
* properly. If the PHY is not recognized, then return 0
|
|
* (failure). Otherwise, return 1
|
|
*/
|
|
static int init_phy(struct tsec_private *priv)
|
|
{
|
|
struct phy_device *phydev;
|
|
struct tsec __iomem *regs = priv->regs;
|
|
u32 supported = (SUPPORTED_10baseT_Half |
|
|
SUPPORTED_10baseT_Full |
|
|
SUPPORTED_100baseT_Half |
|
|
SUPPORTED_100baseT_Full);
|
|
|
|
if (priv->flags & TSEC_GIGABIT)
|
|
supported |= SUPPORTED_1000baseT_Full;
|
|
|
|
/* Assign a Physical address to the TBI */
|
|
out_be32(®s->tbipa, priv->tbiaddr);
|
|
|
|
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
|
|
tsec_configure_serdes(priv);
|
|
|
|
#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
|
|
phydev = dm_eth_phy_connect(priv->dev);
|
|
#else
|
|
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
|
|
priv->interface);
|
|
#endif
|
|
if (!phydev)
|
|
return 0;
|
|
|
|
phydev->supported &= supported;
|
|
phydev->advertising = phydev->supported;
|
|
|
|
priv->phydev = phydev;
|
|
|
|
phy_config(phydev);
|
|
|
|
return 1;
|
|
}
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
/*
|
|
* Initialize device structure. Returns success if PHY
|
|
* initialization succeeded (i.e. if it recognizes the PHY)
|
|
*/
|
|
static int tsec_initialize(struct bd_info *bis,
|
|
struct tsec_info_struct *tsec_info)
|
|
{
|
|
struct tsec_private *priv;
|
|
struct eth_device *dev;
|
|
int i;
|
|
|
|
dev = (struct eth_device *)malloc(sizeof(*dev));
|
|
|
|
if (!dev)
|
|
return 0;
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
priv = (struct tsec_private *)malloc(sizeof(*priv));
|
|
|
|
if (!priv) {
|
|
free(dev);
|
|
return 0;
|
|
}
|
|
|
|
priv->regs = tsec_info->regs;
|
|
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
|
|
|
|
priv->phyaddr = tsec_info->phyaddr;
|
|
priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
|
|
priv->flags = tsec_info->flags;
|
|
|
|
strcpy(dev->name, tsec_info->devname);
|
|
priv->interface = tsec_info->interface;
|
|
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
|
|
priv->dev = dev;
|
|
dev->iobase = 0;
|
|
dev->priv = priv;
|
|
dev->init = tsec_init;
|
|
dev->halt = tsec_halt;
|
|
dev->send = tsec_send;
|
|
dev->recv = tsec_recv;
|
|
dev->mcast = tsec_mcast_addr;
|
|
|
|
/* Tell U-Boot to get the addr from the env */
|
|
for (i = 0; i < 6; i++)
|
|
dev->enetaddr[i] = 0;
|
|
|
|
eth_register(dev);
|
|
|
|
/* Reset the MAC */
|
|
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
|
|
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
|
|
/* Try to initialize PHY here, and return */
|
|
return init_phy(priv);
|
|
}
|
|
|
|
/*
|
|
* Initialize all the TSEC devices
|
|
*
|
|
* Returns the number of TSEC devices that were initialized
|
|
*/
|
|
int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
|
|
int num)
|
|
{
|
|
int i;
|
|
int count = 0;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
int ret = tsec_initialize(bis, &tsecs[i]);
|
|
|
|
if (ret > 0)
|
|
count += ret;
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
int tsec_standard_init(struct bd_info *bis)
|
|
{
|
|
struct fsl_pq_mdio_info info;
|
|
|
|
info.regs = TSEC_GET_MDIO_REGS_BASE(1);
|
|
info.name = DEFAULT_MII_NAME;
|
|
|
|
fsl_pq_mdio_init(bis, &info);
|
|
|
|
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
|
|
}
|
|
#else /* CONFIG_DM_ETH */
|
|
int tsec_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct tsec_private *priv = dev_get_priv(dev);
|
|
struct ofnode_phandle_args phandle_args;
|
|
u32 tbiaddr = CFG_SYS_TBIPA_VALUE;
|
|
struct tsec_data *data;
|
|
ofnode parent, child;
|
|
fdt_addr_t reg;
|
|
u32 max_speed;
|
|
int ret;
|
|
|
|
data = (struct tsec_data *)dev_get_driver_data(dev);
|
|
|
|
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
|
|
if (pdata->iobase == FDT_ADDR_T_NONE) {
|
|
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
|
|
if (strncmp(ofnode_get_name(child), "queue-group",
|
|
strlen("queue-group")))
|
|
continue;
|
|
|
|
reg = ofnode_get_addr(child);
|
|
if (reg == FDT_ADDR_T_NONE) {
|
|
printf("No 'reg' property of <queue-group>\n");
|
|
return -ENOENT;
|
|
}
|
|
pdata->iobase = reg;
|
|
|
|
/*
|
|
* if there are multiple queue groups,
|
|
* only the first one is used.
|
|
*/
|
|
break;
|
|
}
|
|
|
|
if (!ofnode_valid(child)) {
|
|
printf("No child node for <queue-group>?\n");
|
|
return -ENOENT;
|
|
}
|
|
}
|
|
|
|
priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
|
|
|
|
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
|
|
&phandle_args);
|
|
if (ret == 0) {
|
|
ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
|
|
|
|
parent = ofnode_get_parent(phandle_args.node);
|
|
if (!ofnode_valid(parent)) {
|
|
printf("No parent node for TBI PHY?\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
reg = ofnode_get_addr_index(parent, 0);
|
|
if (reg == FDT_ADDR_T_NONE) {
|
|
printf("No 'reg' property of MII for TBI PHY\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
|
|
0, MAP_NOCACHE);
|
|
}
|
|
|
|
priv->tbiaddr = tbiaddr;
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
pdata->phy_interface = tsec_get_interface(priv);
|
|
|
|
priv->interface = pdata->phy_interface;
|
|
|
|
/* Check for speed limit, default is 1000Mbps */
|
|
max_speed = dev_read_u32_default(dev, "max-speed", 1000);
|
|
|
|
/* Initialize flags */
|
|
if (max_speed == 1000)
|
|
priv->flags = TSEC_GIGABIT;
|
|
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
|
|
priv->flags |= TSEC_SGMII;
|
|
|
|
/* Reset the MAC */
|
|
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
|
|
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
|
|
|
|
priv->dev = dev;
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
/* Try to initialize PHY here, and return */
|
|
return !init_phy(priv);
|
|
}
|
|
|
|
int tsec_remove(struct udevice *dev)
|
|
{
|
|
struct tsec_private *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops tsec_ops = {
|
|
.start = tsec_init,
|
|
.send = tsec_send,
|
|
.recv = tsec_recv,
|
|
.free_pkt = tsec_free_pkt,
|
|
.stop = tsec_halt,
|
|
.mcast = tsec_mcast_addr,
|
|
.set_promisc = tsec_set_promisc,
|
|
};
|
|
|
|
static struct tsec_data etsec2_data = {
|
|
.mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
|
|
};
|
|
|
|
static struct tsec_data gianfar_data = {
|
|
.mdio_regs_off = 0x0,
|
|
};
|
|
|
|
static const struct udevice_id tsec_ids[] = {
|
|
{ .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
|
|
{ .compatible = "gianfar", .data = (ulong)&gianfar_data },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_tsec) = {
|
|
.name = "tsec",
|
|
.id = UCLASS_ETH,
|
|
.of_match = tsec_ids,
|
|
.probe = tsec_probe,
|
|
.remove = tsec_remove,
|
|
.ops = &tsec_ops,
|
|
.priv_auto = sizeof(struct tsec_private),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
#endif /* CONFIG_DM_ETH */
|