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https://github.com/AsahiLinux/u-boot
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52503d8135
NPCM750 provides identical ethernet MAC controllers for WAN/LAN applications. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
745 lines
18 KiB
C
745 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <net.h>
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#include <regmap.h>
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#include <serial.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#define MAC_ADDR_SIZE 6
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#define CONFIG_TX_DESCR_NUM 32
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#define CONFIG_RX_DESCR_NUM 32
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#define TX_TOTAL_BUFSIZE \
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((CONFIG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
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#define RX_TOTAL_BUFSIZE \
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((CONFIG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN)
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#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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struct npcm750_rxbd {
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unsigned int sl;
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unsigned int buffer;
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unsigned int reserved;
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unsigned int next;
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} __aligned(ARCH_DMA_MINALIGN);
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struct npcm750_txbd {
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unsigned int mode;
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unsigned int buffer;
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unsigned int sl;
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unsigned int next;
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} __aligned(ARCH_DMA_MINALIGN);
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struct emc_regs {
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u32 camcmr; /* 0x00 */
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u32 camen; /* 0x04 */
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u32 cam0m; /* 0x08 */
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u32 cam0l; /* 0x0c */
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u32 cam1m; /* 0x10 */
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u32 cam1l; /* 0x14 */
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u32 cam2m; /* 0x18 */
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u32 cam2l; /* 0x1c */
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u32 cam3m; /* 0x20 */
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u32 cam3l; /* 0x24 */
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u32 cam4m; /* 0x28 */
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u32 cam4l; /* 0x2c */
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u32 cam5m; /* 0x30 */
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u32 cam5l; /* 0x34 */
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u32 cam6m; /* 0x38 */
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u32 cam6l; /* 0x3c */
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u32 cam7m; /* 0x40 */
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u32 cam7l; /* 0x44 */
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u32 cam8m; /* 0x48 */
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u32 cam8l; /* 0x4c */
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u32 cam9m; /* 0x50 */
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u32 cam9l; /* 0x54 */
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u32 cam10m; /* 0x58 */
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u32 cam10l; /* 0x5c */
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u32 cam11m; /* 0x60 */
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u32 cam11l; /* 0x64 */
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u32 cam12m; /* 0x68 */
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u32 cam12l; /* 0x6c */
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u32 cam13m; /* 0x70 */
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u32 cam13l; /* 0x74 */
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u32 cam14m; /* 0x78 */
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u32 cam14l; /* 0x7c */
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u32 cam15m; /* 0x80 */
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u32 cam15l; /* 0x84 */
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u32 txdlsa; /* 0x88 */
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u32 rxdlsa; /* 0x8c */
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u32 mcmdr; /* 0x90 */
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u32 miid; /* 0x94 */
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u32 miida; /* 0x98 */
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u32 fftcr; /* 0x9c */
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u32 tsdr; /* 0xa0 */
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u32 rsdr; /* 0xa4 */
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u32 dmarfc; /* 0xa8 */
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u32 mien; /* 0xac */
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u32 mista; /* 0xb0 */
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u32 mgsta; /* 0xb4 */
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u32 mpcnt; /* 0xb8 */
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u32 mrpc; /* 0xbc */
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u32 mrpcc; /* 0xc0 */
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u32 mrepc; /* 0xc4 */
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u32 dmarfs; /* 0xc8 */
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u32 ctxdsa; /* 0xcc */
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u32 ctxbsa; /* 0xd0 */
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u32 crxdsa; /* 0xd4 */
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u32 crxbsa; /* 0xd8 */
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};
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struct npcm750_eth_dev {
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struct npcm750_txbd tdesc[CONFIG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
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struct npcm750_rxbd rdesc[CONFIG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN);
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u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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struct emc_regs *emc_regs_p;
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struct phy_device *phydev;
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struct mii_dev *bus;
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struct npcm750_txbd *curr_txd;
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struct npcm750_rxbd *curr_rxd;
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u32 interface;
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u32 max_speed;
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u32 idx;
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struct regmap *gcr_regmap;
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};
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struct npcm750_eth_pdata {
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struct eth_pdata eth_pdata;
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};
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/* mac controller bit */
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#define MCMDR_RXON BIT(0)
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#define MCMDR_ACP BIT(3)
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#define MCMDR_SPCRC BIT(5)
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#define MCMDR_TXON BIT(8)
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#define MCMDR_NDEF BIT(9)
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#define MCMDR_FDUP BIT(18)
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#define MCMDR_ENMDC BIT(19)
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#define MCMDR_OPMOD BIT(20)
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#define MCMDR_SWR BIT(24)
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/* cam command regiser */
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#define CAMCMR_AUP 0x01
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#define CAMCMR_AMP BIT(1)
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#define CAMCMR_ABP BIT(2)
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#define CAMCMR_CCAM BIT(3)
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#define CAMCMR_ECMP BIT(4)
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#define CAM0EN 0x01
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/* mac mii controller bit */
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#define MDCON BIT(19)
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#define PHYAD BIT(8)
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#define PHYWR BIT(16)
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#define PHYBUSY BIT(17)
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#define PHYPRESP BIT(18)
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#define CAM_ENTRY_SIZE 0x08
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/* rx and tx status */
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#define TXDS_TXCP BIT(19)
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#define RXDS_CRCE BIT(17)
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#define RXDS_PTLE BIT(19)
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#define RXDS_RXGD BIT(20)
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#define RXDS_ALIE BIT(21)
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#define RXDS_RP BIT(22)
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/* mac interrupt status*/
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#define MISTA_RXINTR BIT(0)
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#define MISTA_CRCE BIT(1)
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#define MISTA_RXOV BIT(2)
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#define MISTA_PTLE BIT(3)
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#define MISTA_RXGD BIT(4)
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#define MISTA_ALIE BIT(5)
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#define MISTA_RP BIT(6)
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#define MISTA_MMP BIT(7)
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#define MISTA_DFOI BIT(8)
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#define MISTA_DENI BIT(9)
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#define MISTA_RDU BIT(10)
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#define MISTA_RXBERR BIT(11)
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#define MISTA_CFR BIT(14)
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#define MISTA_TXINTR BIT(16)
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#define MISTA_TXEMP BIT(17)
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#define MISTA_TXCP BIT(18)
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#define MISTA_EXDEF BIT(19)
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#define MISTA_NCS BIT(20)
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#define MISTA_TXABT BIT(21)
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#define MISTA_LC BIT(22)
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#define MISTA_TDU BIT(23)
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#define MISTA_TXBERR BIT(24)
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#define ENSTART 0x01
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#define ENRXINTR BIT(0)
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#define ENCRCE BIT(1)
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#define EMRXOV BIT(2)
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#define ENPTLE BIT(3)
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#define ENRXGD BIT(4)
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#define ENALIE BIT(5)
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#define ENRP BIT(6)
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#define ENMMP BIT(7)
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#define ENDFO BIT(8)
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#define ENDENI BIT(9)
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#define ENRDU BIT(10)
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#define ENRXBERR BIT(11)
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#define ENCFR BIT(14)
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#define ENTXINTR BIT(16)
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#define ENTXEMP BIT(17)
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#define ENTXCP BIT(18)
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#define ENTXDEF BIT(19)
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#define ENNCS BIT(20)
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#define ENTXABT BIT(21)
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#define ENLC BIT(22)
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#define ENTDU BIT(23)
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#define ENTXBERR BIT(24)
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#define RX_STAT_RBC 0xffff
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#define RX_STAT_RXINTR BIT(16)
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#define RX_STAT_CRCE BIT(17)
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#define RX_STAT_PTLE BIT(19)
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#define RX_STAT_RXGD BIT(20)
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#define RX_STAT_ALIE BIT(21)
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#define RX_STAT_RP BIT(22)
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#define RX_STAT_OWNER (BIT(30) | BIT(31))
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#define TX_STAT_TBC 0xffff
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#define TX_STAT_TXINTR BIT(16)
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#define TX_STAT_DEF BIT(17)
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#define TX_STAT_TXCP BIT(19)
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#define TX_STAT_EXDEF BIT(20)
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#define TX_STAT_NCS BIT(21)
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#define TX_STAT_TXBT BIT(22)
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#define TX_STAT_LC BIT(23)
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#define TX_STAT_TXHA BIT(24)
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#define TX_STAT_PAU BIT(25)
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#define TX_STAT_SQE BIT(26)
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/* rx and tx owner bit */
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#define RX_OWEN_DMA BIT(31)
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#define RX_OWEN_CPU 0x00 //bit 30 & bit 31
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#define TX_OWEN_DMA BIT(31)
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#define TX_OWEN_CPU (~(BIT(31)))
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/* tx frame desc controller bit */
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#define MACTXINTEN 0x04
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#define CRCMODE 0x02
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#define PADDINGMODE 0x01
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/* fftcr controller bit */
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#define RXTHD 0x03
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#define TXTHD (BIT(8) | BIT(9))
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#define BLENGTH BIT(21)
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/* global setting for driver */
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#define RX_DESC_SIZE 128
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#define TX_DESC_SIZE 64
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#define MAX_RBUFF_SZ 0x600
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#define MAX_TBUFF_SZ 0x600
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#define TX_TIMEOUT 50
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#define DELAY 1000
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#define CAM0 0x0
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#define RX_POLL_SIZE (RX_DESC_SIZE / 2)
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#define MII_TIMEOUT 100
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#define GCR_INTCR 0x3c
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#define INTCR_R1EN BIT(5)
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enum MIIDA_MDCCR_T {
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MIIDA_MDCCR_4 = 0x00,
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MIIDA_MDCCR_6 = 0x01,
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MIIDA_MDCCR_8 = 0x02,
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MIIDA_MDCCR_12 = 0x03,
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MIIDA_MDCCR_16 = 0x04,
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MIIDA_MDCCR_20 = 0x05,
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MIIDA_MDCCR_24 = 0x06,
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MIIDA_MDCCR_28 = 0x07,
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MIIDA_MDCCR_30 = 0x08,
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MIIDA_MDCCR_32 = 0x09,
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MIIDA_MDCCR_36 = 0x0A,
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MIIDA_MDCCR_40 = 0x0B,
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MIIDA_MDCCR_44 = 0x0C,
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MIIDA_MDCCR_48 = 0x0D,
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MIIDA_MDCCR_54 = 0x0E,
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MIIDA_MDCCR_60 = 0x0F,
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};
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DECLARE_GLOBAL_DATA_PTR;
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static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs)
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{
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struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
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struct emc_regs *reg = priv->emc_regs_p;
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u32 start, val;
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int timeout = CONFIG_MDIO_TIMEOUT;
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val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20);
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writel(val, ®->miida);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(®->miida) & PHYBUSY)) {
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val = readl(®->miid);
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return val;
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}
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udelay(10);
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};
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return -ETIMEDOUT;
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}
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static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs,
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u16 val)
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{
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struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv;
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struct emc_regs *reg = priv->emc_regs_p;
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ulong start;
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int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
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writel(val, ®->miid);
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writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), ®->miida);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(®->miida) & PHYBUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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static int npcm750_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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static int npcm750_mdio_init(const char *name, struct npcm750_eth_dev *priv)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -ENOMEM;
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}
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bus->read = npcm750_mdio_read;
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bus->write = npcm750_mdio_write;
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snprintf(bus->name, sizeof(bus->name), "%s", name);
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bus->reset = npcm750_mdio_reset;
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bus->priv = (void *)priv;
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writel(readl(®->mcmdr) | MCMDR_ENMDC, ®->mcmdr);
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return mdio_register(bus);
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}
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static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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struct npcm750_txbd *desc_table_p = &priv->tdesc[0];
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struct npcm750_txbd *desc_p;
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u8 *txbuffs = &priv->txbuffs[0];
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u32 idx;
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writel((u32)desc_table_p, ®->txdlsa);
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priv->curr_txd = desc_table_p;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN];
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desc_p->sl = 0;
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desc_p->mode = 0;
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desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN;
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if (idx < (CONFIG_TX_DESCR_NUM - 1))
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desc_p->next = (u32)&desc_table_p[idx + 1];
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else
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desc_p->next = (u32)&priv->tdesc[0];
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}
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flush_dcache_range((ulong)&desc_table_p[0],
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(ulong)&desc_table_p[CONFIG_TX_DESCR_NUM]);
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}
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static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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struct npcm750_rxbd *desc_table_p = &priv->rdesc[0];
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struct npcm750_rxbd *desc_p;
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u8 *rxbuffs = &priv->rxbuffs[0];
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u32 idx;
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flush_dcache_range((ulong)priv->rxbuffs[0],
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(ulong)priv->rxbuffs[CONFIG_RX_DESCR_NUM]);
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writel((u32)desc_table_p, ®->rxdlsa);
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priv->curr_rxd = desc_table_p;
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->sl = RX_OWEN_DMA;
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desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN];
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if (idx < (CONFIG_RX_DESCR_NUM - 1))
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desc_p->next = (u32)&desc_table_p[idx + 1];
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else
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desc_p->next = (u32)&priv->rdesc[0];
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}
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flush_dcache_range((ulong)&desc_table_p[0],
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(ulong)&desc_table_p[CONFIG_RX_DESCR_NUM]);
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}
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static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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unsigned int val;
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val = RXTHD | TXTHD | BLENGTH;
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writel(val, ®->fftcr);
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}
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static void npcm750_set_global_maccmd(struct npcm750_eth_dev *priv)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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unsigned int val;
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val = readl(®->mcmdr);
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val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | MCMDR_NDEF;
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writel(val, ®->mcmdr);
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}
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static void npcm750_set_cam(struct npcm750_eth_dev *priv,
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unsigned int x, unsigned char *pval)
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{
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struct emc_regs *reg = priv->emc_regs_p;
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unsigned int msw, lsw;
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msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3];
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lsw = (pval[4] << 24) | (pval[5] << 16);
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writel(lsw, ®->cam0l + x * CAM_ENTRY_SIZE);
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writel(msw, ®->cam0m + x * CAM_ENTRY_SIZE);
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writel(readl(®->camen) | CAM0EN, ®->camen);
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writel(CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AUP, ®->camcmr);
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}
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static void npcm750_adjust_link(struct emc_regs *reg,
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struct phy_device *phydev)
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{
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u32 val = readl(®->mcmdr);
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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if (phydev->speed == 100)
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val |= MCMDR_OPMOD;
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else
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val &= ~MCMDR_OPMOD;
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if (phydev->duplex)
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val |= MCMDR_FDUP;
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else
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val &= ~MCMDR_FDUP;
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writel(val, ®->mcmdr);
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debug("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
|
|
|
|
static int npcm750_phy_init(struct npcm750_eth_dev *priv, void *dev)
|
|
{
|
|
struct phy_device *phydev;
|
|
int ret;
|
|
u32 address = 0x0;
|
|
|
|
phydev = phy_connect(priv->bus, address, dev, priv->interface);
|
|
if (!phydev)
|
|
return -ENODEV;
|
|
|
|
if (priv->max_speed) {
|
|
ret = phy_set_supported(phydev, priv->max_speed);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
phydev->advertising = phydev->supported;
|
|
|
|
priv->phydev = phydev;
|
|
phy_config(phydev);
|
|
return 0;
|
|
}
|
|
|
|
static int npcm750_eth_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
u8 *enetaddr = pdata->enetaddr;
|
|
int ret;
|
|
|
|
writel(readl(®->mcmdr) & ~MCMDR_TXON & ~MCMDR_RXON, ®->mcmdr);
|
|
|
|
writel(readl(®->mcmdr) | MCMDR_SWR, ®->mcmdr);
|
|
do {
|
|
ret = readl(®->mcmdr);
|
|
} while (ret & MCMDR_SWR);
|
|
|
|
npcm750_rx_descs_init(priv);
|
|
npcm750_tx_descs_init(priv);
|
|
|
|
npcm750_set_cam(priv, priv->idx, enetaddr);
|
|
npcm750_set_global_maccmd(priv);
|
|
npcm750_set_fifo_threshold(priv);
|
|
|
|
/* Start up the PHY */
|
|
ret = phy_startup(priv->phydev);
|
|
if (ret) {
|
|
printf("Could not initialize PHY\n");
|
|
return ret;
|
|
}
|
|
|
|
npcm750_adjust_link(reg, priv->phydev);
|
|
writel(readl(®->mcmdr) | MCMDR_TXON | MCMDR_RXON, ®->mcmdr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int npcm750_eth_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
struct npcm750_txbd *desc_p;
|
|
struct npcm750_txbd *next_desc_p;
|
|
|
|
desc_p = priv->curr_txd;
|
|
|
|
invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
|
|
/* Check if the descriptor is owned by CPU */
|
|
if (desc_p->mode & TX_OWEN_DMA) {
|
|
next_desc_p = (struct npcm750_txbd *)desc_p->next;
|
|
|
|
while ((next_desc_p != desc_p) && (next_desc_p->mode & TX_OWEN_DMA))
|
|
next_desc_p = (struct npcm750_txbd *)next_desc_p->next;
|
|
|
|
if (next_desc_p == desc_p) {
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
|
|
writel(0, ®->tsdr);
|
|
serial_printf("TX: overflow and exit\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
desc_p = next_desc_p;
|
|
}
|
|
|
|
memcpy((void *)desc_p->buffer, packet, length);
|
|
flush_dcache_range((ulong)desc_p->buffer,
|
|
(ulong)desc_p->buffer + roundup(length, ARCH_DMA_MINALIGN));
|
|
desc_p->sl = 0;
|
|
desc_p->sl = length & TX_STAT_TBC;
|
|
desc_p->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE;
|
|
flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
|
|
|
|
if (!(readl(®->mcmdr) & MCMDR_TXON))
|
|
writel(readl(®->mcmdr) | MCMDR_TXON, ®->mcmdr);
|
|
priv->curr_txd = (struct npcm750_txbd *)priv->curr_txd->next;
|
|
|
|
writel(0, ®->tsdr);
|
|
return 0;
|
|
}
|
|
|
|
static int npcm750_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
struct npcm750_rxbd *desc_p;
|
|
struct npcm750_rxbd *next_desc_p;
|
|
int length = -1;
|
|
|
|
desc_p = priv->curr_rxd;
|
|
invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
|
|
|
|
if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_DMA) {
|
|
next_desc_p = (struct npcm750_rxbd *)desc_p->next;
|
|
while ((next_desc_p != desc_p) &&
|
|
((next_desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU)) {
|
|
next_desc_p = (struct npcm750_rxbd *)next_desc_p->next;
|
|
}
|
|
|
|
if (next_desc_p == desc_p) {
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
|
|
writel(0, ®->rsdr);
|
|
serial_printf("RX: overflow and exit\n");
|
|
return -EPERM;
|
|
}
|
|
desc_p = next_desc_p;
|
|
}
|
|
|
|
/* Check if the descriptor is owned by CPU */
|
|
if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU) {
|
|
if (desc_p->sl & RX_STAT_RXGD) {
|
|
length = desc_p->sl & RX_STAT_RBC;
|
|
invalidate_dcache_range((ulong)desc_p->buffer,
|
|
(ulong)(desc_p->buffer + roundup(length,
|
|
ARCH_DMA_MINALIGN)));
|
|
*packetp = (u8 *)(u32)desc_p->buffer;
|
|
priv->curr_rxd = desc_p;
|
|
}
|
|
}
|
|
return length;
|
|
}
|
|
|
|
static int npcm750_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
struct npcm750_rxbd *desc_p = priv->curr_rxd;
|
|
|
|
/*
|
|
* Make the current descriptor valid again and go to
|
|
* the next one
|
|
*/
|
|
desc_p->sl |= RX_OWEN_DMA;
|
|
flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1));
|
|
priv->curr_rxd = (struct npcm750_rxbd *)priv->curr_rxd->next;
|
|
writel(0, ®->rsdr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void npcm750_eth_stop(struct udevice *dev)
|
|
{
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
struct emc_regs *reg = priv->emc_regs_p;
|
|
|
|
writel(readl(®->mcmdr) & ~MCMDR_TXON, ®->mcmdr);
|
|
writel(readl(®->mcmdr) & ~MCMDR_RXON, ®->mcmdr);
|
|
priv->curr_txd = (struct npcm750_txbd *)readl(®->txdlsa);
|
|
priv->curr_rxd = (struct npcm750_rxbd *)readl(®->rxdlsa);
|
|
phy_shutdown(priv->phydev);
|
|
}
|
|
|
|
static int npcm750_eth_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
npcm750_set_cam(priv, CAM0, pdata->enetaddr);
|
|
return 0;
|
|
}
|
|
|
|
static int npcm750_eth_bind(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int npcm750_eth_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
u32 iobase = pdata->iobase;
|
|
int ret;
|
|
|
|
memset(priv, 0, sizeof(struct npcm750_eth_dev));
|
|
ret = dev_read_u32(dev, "id", &priv->idx);
|
|
if (ret) {
|
|
printf("failed to get id\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
|
|
if (IS_ERR(priv->gcr_regmap))
|
|
return -EINVAL;
|
|
|
|
priv->emc_regs_p = (struct emc_regs *)iobase;
|
|
priv->interface = pdata->phy_interface;
|
|
priv->max_speed = pdata->max_speed;
|
|
|
|
if (priv->idx == 0) {
|
|
/* Enable RMII for EMC1 module */
|
|
regmap_update_bits(priv->gcr_regmap, GCR_INTCR, INTCR_R1EN, INTCR_R1EN);
|
|
}
|
|
|
|
npcm750_mdio_init(dev->name, priv);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
ret = npcm750_phy_init(priv, dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int npcm750_eth_remove(struct udevice *dev)
|
|
{
|
|
struct npcm750_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops npcm750_eth_ops = {
|
|
.start = npcm750_eth_start,
|
|
.send = npcm750_eth_send,
|
|
.recv = npcm750_eth_recv,
|
|
.free_pkt = npcm750_eth_free_pkt,
|
|
.stop = npcm750_eth_stop,
|
|
.write_hwaddr = npcm750_eth_write_hwaddr,
|
|
};
|
|
|
|
static int npcm750_eth_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct npcm750_eth_pdata *npcm750_pdata = dev_get_plat(dev);
|
|
struct eth_pdata *pdata = &npcm750_pdata->eth_pdata;
|
|
const char *phy_mode;
|
|
const fdt32_t *cell;
|
|
int ret = 0;
|
|
|
|
pdata->iobase = (phys_addr_t)dev_read_addr_ptr(dev);
|
|
|
|
pdata->phy_interface = -1;
|
|
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL);
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdata->max_speed = 0;
|
|
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
|
|
if (cell)
|
|
pdata->max_speed = fdt32_to_cpu(*cell);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id npcm750_eth_ids[] = {
|
|
{ .compatible = "nuvoton,npcm750-emc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_npcm750) = {
|
|
.name = "eth_npcm750",
|
|
.id = UCLASS_ETH,
|
|
.of_match = npcm750_eth_ids,
|
|
.of_to_plat = npcm750_eth_ofdata_to_platdata,
|
|
.bind = npcm750_eth_bind,
|
|
.probe = npcm750_eth_probe,
|
|
.remove = npcm750_eth_remove,
|
|
.ops = &npcm750_eth_ops,
|
|
.priv_auto = sizeof(struct npcm750_eth_dev),
|
|
.plat_auto = sizeof(struct npcm750_eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|