mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
f10643cf8a
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm IPQ4019 MDIO driver
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*
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* Copyright (c) 2020 Sartura Ltd.
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*
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* Author: Luka Kovacic <luka.kovacic@sartura.hr>
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* Author: Robert Marko <robert.marko@sartura.hr>
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*
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* Based on Linux driver
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include <miiphy.h>
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#include <phy.h>
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#define MDIO_MODE_REG 0x40
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#define MDIO_ADDR_REG 0x44
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#define MDIO_DATA_WRITE_REG 0x48
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#define MDIO_DATA_READ_REG 0x4c
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#define MDIO_CMD_REG 0x50
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#define MDIO_CMD_ACCESS_BUSY BIT(16)
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#define MDIO_CMD_ACCESS_START BIT(8)
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#define MDIO_CMD_ACCESS_CODE_READ 0
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#define MDIO_CMD_ACCESS_CODE_WRITE 1
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/* 0 = Clause 22, 1 = Clause 45 */
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#define MDIO_MODE_BIT BIT(8)
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#define IPQ4019_MDIO_TIMEOUT 10000
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#define IPQ4019_MDIO_SLEEP 10
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struct ipq4019_mdio_priv {
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phys_addr_t mdio_base;
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};
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static int ipq4019_mdio_wait_busy(struct ipq4019_mdio_priv *priv)
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{
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unsigned int busy;
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return readl_poll_sleep_timeout(priv->mdio_base + MDIO_CMD_REG, busy,
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(busy & MDIO_CMD_ACCESS_BUSY) == 0, IPQ4019_MDIO_SLEEP,
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IPQ4019_MDIO_TIMEOUT);
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}
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int ipq4019_mdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
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unsigned int cmd;
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if (ipq4019_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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/* Issue the phy address and reg */
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writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
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/* Issue read command */
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writel(cmd, priv->mdio_base + MDIO_CMD_REG);
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/* Wait read complete */
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if (ipq4019_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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/* Read and return data */
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return readl(priv->mdio_base + MDIO_DATA_READ_REG);
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}
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int ipq4019_mdio_write(struct udevice *dev, int addr, int devad,
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int reg, u16 val)
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{
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struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
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unsigned int cmd;
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if (ipq4019_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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/* Issue the phy addreass and reg */
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writel((addr << 8) | reg, priv->mdio_base + MDIO_ADDR_REG);
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/* Issue write data */
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writel(val, priv->mdio_base + MDIO_DATA_WRITE_REG);
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cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
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/* Issue write command */
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writel(cmd, priv->mdio_base + MDIO_CMD_REG);
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/* Wait for write complete */
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if (ipq4019_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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return 0;
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}
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static const struct mdio_ops ipq4019_mdio_ops = {
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.read = ipq4019_mdio_read,
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.write = ipq4019_mdio_write,
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};
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static int ipq4019_mdio_bind(struct udevice *dev)
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{
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if (ofnode_valid(dev_ofnode(dev)))
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device_set_name(dev, ofnode_get_name(dev_ofnode(dev)));
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return 0;
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}
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static int ipq4019_mdio_probe(struct udevice *dev)
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{
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struct ipq4019_mdio_priv *priv = dev_get_priv(dev);
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unsigned int data;
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priv->mdio_base = dev_read_addr(dev);
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if (priv->mdio_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Enter Clause 22 mode */
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data = readl(priv->mdio_base + MDIO_MODE_REG);
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data &= ~MDIO_MODE_BIT;
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writel(data, priv->mdio_base + MDIO_MODE_REG);
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return 0;
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}
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static const struct udevice_id ipq4019_mdio_ids[] = {
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{ .compatible = "qcom,ipq4019-mdio", },
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{ }
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};
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U_BOOT_DRIVER(ipq4019_mdio) = {
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.name = "ipq4019_mdio",
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.id = UCLASS_MDIO,
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.of_match = ipq4019_mdio_ids,
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.bind = ipq4019_mdio_bind,
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.probe = ipq4019_mdio_probe,
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.ops = &ipq4019_mdio_ops,
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.priv_auto = sizeof(struct ipq4019_mdio_priv),
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};
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