mirror of
https://github.com/AsahiLinux/u-boot
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3b400e84ba
Update the ftgmac100 driver to support NC-SI instead of an mdio phy where available. This is a common setup for Aspeed AST2x00 platforms. NC-SI mode is determined from the device-tree if either phy-mode sets it or the use-ncsi property exists. If set then normal mdio setup is skipped in favour of the NC-SI phy. Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
663 lines
16 KiB
C
663 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Faraday FTGMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* (C) Copyright 2010 Andes Technology
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* Macpaul Lin <macpaul@andestech.com>
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*
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* Copyright (C) 2018, IBM Corporation.
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <wait_bit.h>
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#include <asm/cache.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "ftgmac100.h"
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/* Min frame ethernet frame size without FCS */
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#define ETH_ZLEN 60
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/* Receive Buffer Size Register - HW default is 0x640 */
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#define FTGMAC100_RBSR_DEFAULT 0x640
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/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
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#define PKTBUFSTX 4 /* must be power of 2 */
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/* Timeout for transmit */
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#define FTGMAC100_TX_TIMEOUT_MS 1000
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/* Timeout for a mdio read/write operation */
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#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
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/*
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* MDC clock cycle threshold
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*
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* 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
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*/
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#define MDC_CYCTHR 0x34
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/*
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* ftgmac100 model variants
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*/
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enum ftgmac100_model {
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FTGMAC100_MODEL_FARADAY,
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FTGMAC100_MODEL_ASPEED,
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};
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/**
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* struct ftgmac100_data - private data for the FTGMAC100 driver
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*
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* @iobase: The base address of the hardware registers
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* @txdes: The array of transmit descriptors
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* @rxdes: The array of receive descriptors
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* @tx_index: Transmit descriptor index in @txdes
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* @rx_index: Receive descriptor index in @rxdes
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* @phy_addr: The PHY interface address to use
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* @phydev: The PHY device backing the MAC
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* @bus: The mdio bus
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* @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
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* @max_speed: Maximum speed of Ethernet connection supported by MAC
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* @clks: The bulk of clocks assigned to the device in the DT
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* @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
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* @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
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*/
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struct ftgmac100_data {
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struct ftgmac100 *iobase;
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struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
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struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
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int tx_index;
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int rx_index;
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u32 phy_addr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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u32 phy_mode;
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u32 max_speed;
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struct clk_bulk clks;
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/* End of RX/TX ring buffer bits. Depend on model */
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u32 rxdes0_edorr_mask;
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u32 txdes0_edotr_mask;
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};
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/*
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* struct mii_bus functions
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*/
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static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
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int reg_addr)
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{
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struct ftgmac100_data *priv = bus->priv;
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struct ftgmac100 *ftgmac100 = priv->iobase;
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int phycr;
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int data;
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int ret;
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phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
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FTGMAC100_PHYCR_PHYAD(phy_addr) |
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FTGMAC100_PHYCR_REGAD(reg_addr) |
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FTGMAC100_PHYCR_MIIRD;
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writel(phycr, &ftgmac100->phycr);
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ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
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!(phycr & FTGMAC100_PHYCR_MIIRD),
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FTGMAC100_MDIO_TIMEOUT_USEC);
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if (ret) {
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pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
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bus->name, phy_addr, reg_addr);
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return ret;
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}
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data = readl(&ftgmac100->phydata);
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return FTGMAC100_PHYDATA_MIIRDATA(data);
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}
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static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
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int reg_addr, u16 value)
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{
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struct ftgmac100_data *priv = bus->priv;
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struct ftgmac100 *ftgmac100 = priv->iobase;
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int phycr;
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int data;
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int ret;
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phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
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FTGMAC100_PHYCR_PHYAD(phy_addr) |
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FTGMAC100_PHYCR_REGAD(reg_addr) |
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FTGMAC100_PHYCR_MIIWR;
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data = FTGMAC100_PHYDATA_MIIWDATA(value);
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writel(data, &ftgmac100->phydata);
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writel(phycr, &ftgmac100->phycr);
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ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
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!(phycr & FTGMAC100_PHYCR_MIIWR),
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FTGMAC100_MDIO_TIMEOUT_USEC);
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if (ret) {
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pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
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bus->name, phy_addr, reg_addr);
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}
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return ret;
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}
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static int ftgmac100_mdio_init(struct udevice *dev)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct mii_dev *bus;
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int ret;
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bus = mdio_alloc();
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if (!bus)
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return -ENOMEM;
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bus->read = ftgmac100_mdio_read;
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bus->write = ftgmac100_mdio_write;
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bus->priv = priv;
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ret = mdio_register_seq(bus, dev_seq(dev));
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if (ret) {
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free(bus);
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return ret;
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}
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priv->bus = bus;
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return 0;
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}
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static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
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{
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struct ftgmac100 *ftgmac100 = priv->iobase;
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struct phy_device *phydev = priv->phydev;
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u32 maccr;
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if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
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dev_err(phydev->dev, "No link\n");
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return -EREMOTEIO;
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}
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/* read MAC control register and clear related bits */
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maccr = readl(&ftgmac100->maccr) &
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~(FTGMAC100_MACCR_GIGA_MODE |
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FTGMAC100_MACCR_FAST_MODE |
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FTGMAC100_MACCR_FULLDUP);
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if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
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maccr |= FTGMAC100_MACCR_GIGA_MODE;
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if (phydev->speed == 100)
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maccr |= FTGMAC100_MACCR_FAST_MODE;
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if (phydev->duplex)
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maccr |= FTGMAC100_MACCR_FULLDUP;
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/* update MII config into maccr */
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writel(maccr, &ftgmac100->maccr);
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return 0;
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}
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static int ftgmac100_phy_init(struct udevice *dev)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct phy_device *phydev;
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int ret;
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if (IS_ENABLED(CONFIG_DM_MDIO))
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phydev = dm_eth_phy_connect(dev);
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else
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phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
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if (!phydev)
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return -ENODEV;
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if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
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phydev->supported &= PHY_GBIT_FEATURES;
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if (priv->max_speed) {
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ret = phy_set_supported(phydev, priv->max_speed);
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if (ret)
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return ret;
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}
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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return 0;
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}
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/*
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* Reset MAC
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*/
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static void ftgmac100_reset(struct ftgmac100_data *priv)
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{
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struct ftgmac100 *ftgmac100 = priv->iobase;
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debug("%s()\n", __func__);
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setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
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while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
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;
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}
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/*
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* Set MAC address
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*/
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static int ftgmac100_set_mac(struct ftgmac100_data *priv,
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const unsigned char *mac)
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{
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struct ftgmac100 *ftgmac100 = priv->iobase;
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unsigned int maddr = mac[0] << 8 | mac[1];
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unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
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debug("%s(%x %x)\n", __func__, maddr, laddr);
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writel(maddr, &ftgmac100->mac_madr);
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writel(laddr, &ftgmac100->mac_ladr);
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return 0;
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}
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/*
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* Get MAC address
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*/
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static int ftgmac100_get_mac(struct ftgmac100_data *priv,
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unsigned char *mac)
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{
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struct ftgmac100 *ftgmac100 = priv->iobase;
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unsigned int maddr = readl(&ftgmac100->mac_madr);
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unsigned int laddr = readl(&ftgmac100->mac_ladr);
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debug("%s(%x %x)\n", __func__, maddr, laddr);
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mac[0] = (maddr >> 8) & 0xff;
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mac[1] = maddr & 0xff;
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mac[2] = (laddr >> 24) & 0xff;
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mac[3] = (laddr >> 16) & 0xff;
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mac[4] = (laddr >> 8) & 0xff;
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mac[5] = laddr & 0xff;
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return 0;
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}
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/*
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* disable transmitter, receiver
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*/
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static void ftgmac100_stop(struct udevice *dev)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100 *ftgmac100 = priv->iobase;
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debug("%s()\n", __func__);
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writel(0, &ftgmac100->maccr);
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if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
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phy_shutdown(priv->phydev);
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}
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static int ftgmac100_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_plat(dev);
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100 *ftgmac100 = priv->iobase;
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struct phy_device *phydev = priv->phydev;
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unsigned int maccr;
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ulong start, end;
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int ret;
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int i;
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debug("%s()\n", __func__);
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ftgmac100_reset(priv);
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/* set the ethernet address */
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ftgmac100_set_mac(priv, plat->enetaddr);
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/* disable all interrupts */
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writel(0, &ftgmac100->ier);
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/* initialize descriptors */
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priv->tx_index = 0;
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priv->rx_index = 0;
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for (i = 0; i < PKTBUFSTX; i++) {
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priv->txdes[i].txdes3 = 0;
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priv->txdes[i].txdes0 = 0;
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}
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priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
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start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
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end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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for (i = 0; i < PKTBUFSRX; i++) {
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priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
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priv->rxdes[i].rxdes0 = 0;
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}
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priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
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start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
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end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
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flush_dcache_range(start, end);
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/* transmit ring */
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writel((u32)priv->txdes, &ftgmac100->txr_badr);
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/* receive ring */
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writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
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/* poll receive descriptor automatically */
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writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
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/* config receive buffer size register */
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writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
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/* enable transmitter, receiver */
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maccr = FTGMAC100_MACCR_TXMAC_EN |
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FTGMAC100_MACCR_RXMAC_EN |
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FTGMAC100_MACCR_TXDMA_EN |
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FTGMAC100_MACCR_RXDMA_EN |
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FTGMAC100_MACCR_CRC_APD |
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FTGMAC100_MACCR_FULLDUP |
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FTGMAC100_MACCR_RX_RUNT |
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FTGMAC100_MACCR_RX_BROADPKT;
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writel(maccr, &ftgmac100->maccr);
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ret = phy_startup(phydev);
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if (ret) {
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dev_err(phydev->dev, "Could not start PHY\n");
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return ret;
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}
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ret = ftgmac100_phy_adjust_link(priv);
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if (ret) {
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dev_err(phydev->dev, "Could not adjust link\n");
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return ret;
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}
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printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
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phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
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return 0;
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}
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static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
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ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
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ulong des_end = des_start +
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roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
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/* Release buffer to DMA and flush descriptor */
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curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
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flush_dcache_range(des_start, des_end);
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/* Move to next descriptor */
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priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
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return 0;
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}
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/*
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* Get a data block via Ethernet
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*/
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static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
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unsigned short rxlen;
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ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
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ulong des_end = des_start +
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roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
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ulong data_start = curr_des->rxdes3;
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ulong data_end;
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invalidate_dcache_range(des_start, des_end);
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if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
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return -EAGAIN;
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if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
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FTGMAC100_RXDES0_CRC_ERR |
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FTGMAC100_RXDES0_FTL |
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FTGMAC100_RXDES0_RUNT |
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FTGMAC100_RXDES0_RX_ODD_NB)) {
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return -EAGAIN;
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}
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rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
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debug("%s(): RX buffer %d, %x received\n",
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__func__, priv->rx_index, rxlen);
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/* Invalidate received data */
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data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(data_start, data_end);
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*packetp = (uchar *)data_start;
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return rxlen;
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}
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static u32 ftgmac100_read_txdesc(const void *desc)
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{
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const struct ftgmac100_txdes *txdes = desc;
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ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
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ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
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invalidate_dcache_range(des_start, des_end);
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return txdes->txdes0;
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}
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BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
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/*
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* Send a data block via Ethernet
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*/
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static int ftgmac100_send(struct udevice *dev, void *packet, int length)
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{
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struct ftgmac100_data *priv = dev_get_priv(dev);
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struct ftgmac100 *ftgmac100 = priv->iobase;
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struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
|
|
ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
|
|
ulong des_end = des_start +
|
|
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
|
|
ulong data_start;
|
|
ulong data_end;
|
|
int rc;
|
|
|
|
invalidate_dcache_range(des_start, des_end);
|
|
|
|
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
|
|
dev_err(dev, "no TX descriptor available\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
debug("%s(%x, %x)\n", __func__, (int)packet, length);
|
|
|
|
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
|
|
|
|
curr_des->txdes3 = (unsigned int)packet;
|
|
|
|
/* Flush data to be sent */
|
|
data_start = curr_des->txdes3;
|
|
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
|
|
flush_dcache_range(data_start, data_end);
|
|
|
|
/* Only one segment on TXBUF */
|
|
curr_des->txdes0 &= priv->txdes0_edotr_mask;
|
|
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
|
|
FTGMAC100_TXDES0_LTS |
|
|
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
|
|
FTGMAC100_TXDES0_TXDMA_OWN ;
|
|
|
|
/* Flush modified buffer descriptor */
|
|
flush_dcache_range(des_start, des_end);
|
|
|
|
/* Start transmit */
|
|
writel(1, &ftgmac100->txpd);
|
|
|
|
rc = wait_for_bit_ftgmac100_txdone(curr_des,
|
|
FTGMAC100_TXDES0_TXDMA_OWN, false,
|
|
FTGMAC100_TX_TIMEOUT_MS, true);
|
|
if (rc)
|
|
return rc;
|
|
|
|
debug("%s(): packet sent\n", __func__);
|
|
|
|
/* Move to next descriptor */
|
|
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ftgmac100_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ftgmac100_data *priv = dev_get_priv(dev);
|
|
|
|
return ftgmac100_set_mac(priv, pdata->enetaddr);
|
|
}
|
|
|
|
static int ftgmac_read_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ftgmac100_data *priv = dev_get_priv(dev);
|
|
|
|
return ftgmac100_get_mac(priv, pdata->enetaddr);
|
|
}
|
|
|
|
static int ftgmac100_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ftgmac100_data *priv = dev_get_priv(dev);
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
|
|
|
|
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
|
|
priv->rxdes0_edorr_mask = BIT(30);
|
|
priv->txdes0_edotr_mask = BIT(30);
|
|
} else {
|
|
priv->rxdes0_edorr_mask = BIT(15);
|
|
priv->txdes0_edotr_mask = BIT(15);
|
|
}
|
|
|
|
return clk_get_bulk(dev, &priv->clks);
|
|
}
|
|
|
|
static int ftgmac100_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ftgmac100_data *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
priv->iobase = (struct ftgmac100 *)pdata->iobase;
|
|
priv->phy_mode = pdata->phy_interface;
|
|
priv->max_speed = pdata->max_speed;
|
|
priv->phy_addr = 0;
|
|
|
|
if (dev_read_bool(dev, "use-ncsi"))
|
|
priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
|
|
|
|
#ifdef CONFIG_PHY_ADDR
|
|
priv->phy_addr = CONFIG_PHY_ADDR;
|
|
#endif
|
|
|
|
ret = clk_enable_bulk(&priv->clks);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/*
|
|
* If DM MDIO is enabled, the MDIO bus will be initialized later in
|
|
* dm_eth_phy_connect
|
|
*/
|
|
if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
|
|
!IS_ENABLED(CONFIG_DM_MDIO)) {
|
|
ret = ftgmac100_mdio_init(dev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
ret = ftgmac100_phy_init(dev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize PHY: %d\n", ret);
|
|
goto out;
|
|
}
|
|
|
|
ftgmac_read_hwaddr(dev);
|
|
|
|
out:
|
|
if (ret)
|
|
clk_release_bulk(&priv->clks);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ftgmac100_remove(struct udevice *dev)
|
|
{
|
|
struct ftgmac100_data *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
clk_release_bulk(&priv->clks);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops ftgmac100_ops = {
|
|
.start = ftgmac100_start,
|
|
.send = ftgmac100_send,
|
|
.recv = ftgmac100_recv,
|
|
.stop = ftgmac100_stop,
|
|
.free_pkt = ftgmac100_free_pkt,
|
|
.write_hwaddr = ftgmac100_write_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id ftgmac100_ids[] = {
|
|
{ .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
|
|
{ .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
|
|
{ .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ftgmac100) = {
|
|
.name = "ftgmac100",
|
|
.id = UCLASS_ETH,
|
|
.of_match = ftgmac100_ids,
|
|
.of_to_plat = ftgmac100_of_to_plat,
|
|
.probe = ftgmac100_probe,
|
|
.remove = ftgmac100_remove,
|
|
.ops = &ftgmac100_ops,
|
|
.priv_auto = sizeof(struct ftgmac100_data),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|