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ecd8b03713
Assign packet pointer only in case the MAC reports anything in the FIFO. In case the MAC indicates empty FIFO, return 0 to pass that information to the network stack. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
749 lines
19 KiB
C
749 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dm9000.c: Version 1.2 12/15/2003
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*
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* A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
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* Copyright (C) 1997 Sten Wang
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*
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* (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
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*
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* V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
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* 06/22/2001 Support DM9801 progrmming
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* E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
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* E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
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* R17 = (R17 & 0xfff0) | NF + 3
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* E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
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* R17 = (R17 & 0xfff0) | NF
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*
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* v1.00 modify by simon 2001.9.5
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* change for kernel 2.4.x
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*
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* v1.1 11/09/2001 fix force mode bug
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*
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* v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
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* Fixed phy reset.
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* Added tx/rx 32 bit mode.
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* Cleaned up for kernel merge.
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*
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* --------------------------------------
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*
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* 12/15/2003 Initial port to u-boot by
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* Sascha Hauer <saschahauer@web.de>
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*
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* 06/03/2008 Remy Bohmer <linux@bohmer.net>
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* - Fixed the driver to work with DM9000A.
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* (check on ISR receive status bit before reading the
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* FIFO as described in DM9000 programming guide and
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* application notes)
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* - Added autodetect of databus width.
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* - Made debug code compile again.
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* - Adapt eth_send such that it matches the DM9000*
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* application notes. Needed to make it work properly
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* for DM9000A.
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* - Adapted reset procedure to match DM9000 application
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* notes (i.e. double reset)
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* - some minor code cleanups
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* These changes are tested with DM9000{A,EP,E} together
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* with a 200MHz Atmel AT91SAM9261 core
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*
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* TODO: external MII is not functional, only internal at the moment.
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "dm9000x.h"
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/* Structure/enum declaration ------------------------------- */
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struct dm9000_priv {
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u32 runt_length_counter; /* counter: RX length < 64byte */
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u32 long_length_counter; /* counter: RX length > 1514byte */
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u32 reset_counter; /* counter: RESET */
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u32 reset_tx_timeout; /* RESET caused by TX Timeout */
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u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
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u16 tx_pkt_cnt;
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u16 queue_start_addr;
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u16 dbug_cnt;
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u8 phy_addr;
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u8 device_wait_reset; /* device state */
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unsigned char srom[128];
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void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count);
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void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count);
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void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen);
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#ifndef CONFIG_DM_ETH
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struct eth_device dev;
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#endif
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void __iomem *base_io;
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void __iomem *base_data;
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};
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/* DM9000 network board routine ---------------------------- */
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#ifndef CONFIG_DM9000_BYTE_SWAPPED
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#define dm9000_outb(d, r) writeb((d), (r))
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#define dm9000_outw(d, r) writew((d), (r))
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#define dm9000_outl(d, r) writel((d), (r))
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#define dm9000_inb(r) readb(r)
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#define dm9000_inw(r) readw(r)
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#define dm9000_inl(r) readl(r)
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#else
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#define dm9000_outb(d, r) __raw_writeb(d, r)
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#define dm9000_outw(d, r) __raw_writew(d, r)
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#define dm9000_outl(d, r) __raw_writel(d, r)
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#define dm9000_inb(r) __raw_readb(r)
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#define dm9000_inw(r) __raw_readw(r)
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#define dm9000_inl(r) __raw_readl(r)
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#endif
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#ifdef DEBUG
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static void dm9000_dump_packet(const char *func, u8 *packet, int length)
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{
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int i;
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printf("%s: length: %d\n", func, length);
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for (i = 0; i < length; i++) {
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if (i % 8 == 0)
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printf("\n%s: %02x: ", func, i);
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printf("%02x ", packet[i]);
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}
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printf("\n");
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}
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#else
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static void dm9000_dump_packet(const char *func, u8 *packet, int length) {}
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#endif
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static void dm9000_outblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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dm9000_outb((((u8 *)data_ptr)[i] & 0xff), db->base_data);
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}
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static void dm9000_outblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 1) / 2;
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for (i = 0; i < tmplen; i++)
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dm9000_outw(((u16 *)data_ptr)[i], db->base_data);
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}
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static void dm9000_outblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 3) / 4;
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for (i = 0; i < tmplen; i++)
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dm9000_outl(((u32 *)data_ptr)[i], db->base_data);
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}
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static void dm9000_inblk_8bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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((u8 *)data_ptr)[i] = dm9000_inb(db->base_data);
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}
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static void dm9000_inblk_16bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 1) / 2;
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for (i = 0; i < tmplen; i++)
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((u16 *)data_ptr)[i] = dm9000_inw(db->base_data);
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}
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static void dm9000_inblk_32bit(struct dm9000_priv *db, void *data_ptr, int count)
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{
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int i;
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u32 tmplen = (count + 3) / 4;
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for (i = 0; i < tmplen; i++)
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((u32 *)data_ptr)[i] = dm9000_inl(db->base_data);
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}
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static void dm9000_rx_status_32bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
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{
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u32 tmpdata;
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dm9000_outb(DM9000_MRCMD, db->base_io);
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tmpdata = dm9000_inl(db->base_data);
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*rxstatus = __le16_to_cpu(tmpdata);
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*rxlen = __le16_to_cpu(tmpdata >> 16);
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}
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static void dm9000_rx_status_16bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
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{
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dm9000_outb(DM9000_MRCMD, db->base_io);
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*rxstatus = __le16_to_cpu(dm9000_inw(db->base_data));
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*rxlen = __le16_to_cpu(dm9000_inw(db->base_data));
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}
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static void dm9000_rx_status_8bit(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen)
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{
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dm9000_outb(DM9000_MRCMD, db->base_io);
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*rxstatus =
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__le16_to_cpu(dm9000_inb(db->base_data) +
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(dm9000_inb(db->base_data) << 8));
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*rxlen =
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__le16_to_cpu(dm9000_inb(db->base_data) +
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(dm9000_inb(db->base_data) << 8));
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}
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/*
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* Read a byte from I/O port
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*/
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static u8 dm9000_ior(struct dm9000_priv *db, int reg)
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{
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dm9000_outb(reg, db->base_io);
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return dm9000_inb(db->base_data);
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}
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/*
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* Write a byte to I/O port
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*/
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static void dm9000_iow(struct dm9000_priv *db, int reg, u8 value)
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{
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dm9000_outb(reg, db->base_io);
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dm9000_outb(value, db->base_data);
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}
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/*
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* Read a word from phyxcer
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*/
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static u16 dm9000_phy_read(struct dm9000_priv *db, int reg)
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{
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u16 val;
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/* Fill the phyxcer register into REG_0C */
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dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
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dm9000_iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
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udelay(100); /* Wait read complete */
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dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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val = (dm9000_ior(db, DM9000_EPDRH) << 8) |
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dm9000_ior(db, DM9000_EPDRL);
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/* The read data keeps on REG_0D & REG_0E */
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debug("%s(0x%x): 0x%x\n", __func__, reg, val);
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return val;
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}
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/*
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* Write a word to phyxcer
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*/
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static void dm9000_phy_write(struct dm9000_priv *db, int reg, u16 value)
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{
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/* Fill the phyxcer register into REG_0C */
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dm9000_iow(db, DM9000_EPAR, DM9000_PHY | reg);
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/* Fill the written data into REG_0D & REG_0E */
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dm9000_iow(db, DM9000_EPDRL, (value & 0xff));
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dm9000_iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
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dm9000_iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
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udelay(500); /* Wait write complete */
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dm9000_iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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debug("%s(reg:0x%x, value:0x%x)\n", __func__, reg, value);
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}
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/*
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* Search DM9000 board, allocate space and register it
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*/
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static int dm9000_probe(struct dm9000_priv *db)
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{
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u32 id_val;
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id_val = dm9000_ior(db, DM9000_VIDL);
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id_val |= dm9000_ior(db, DM9000_VIDH) << 8;
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id_val |= dm9000_ior(db, DM9000_PIDL) << 16;
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id_val |= dm9000_ior(db, DM9000_PIDH) << 24;
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if (id_val != DM9000_ID) {
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printf("dm9000 not found at 0x%p id: 0x%08x\n",
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db->base_io, id_val);
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return -1;
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}
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printf("dm9000 i/o: 0x%p, id: 0x%x\n", db->base_io, id_val);
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return 0;
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}
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/* General Purpose dm9000 reset routine */
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static void dm9000_reset(struct dm9000_priv *db)
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{
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debug("resetting DM9000\n");
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/*
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* Reset DM9000,
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* see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
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*/
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/* DEBUG: Make all GPIO0 outputs, all others inputs */
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dm9000_iow(db, DM9000_GPCR, GPCR_GPIO0_OUT);
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/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
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dm9000_iow(db, DM9000_GPR, 0);
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/* Step 2: Software reset */
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dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
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do {
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debug("resetting the DM9000, 1st reset\n");
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udelay(25); /* Wait at least 20 us */
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} while (dm9000_ior(db, DM9000_NCR) & 1);
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dm9000_iow(db, DM9000_NCR, 0);
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dm9000_iow(db, DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
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do {
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debug("resetting the DM9000, 2nd reset\n");
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udelay(25); /* Wait at least 20 us */
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} while (dm9000_ior(db, DM9000_NCR) & 1);
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/* Check whether the ethernet controller is present */
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if ((dm9000_ior(db, DM9000_PIDL) != 0x0) ||
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(dm9000_ior(db, DM9000_PIDH) != 0x90))
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printf("ERROR: resetting DM9000 -> not responding\n");
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}
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/* Initialize dm9000 board */
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static int dm9000_init_common(struct dm9000_priv *db, u8 enetaddr[6])
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{
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int i, oft, lnk;
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u8 io_mode;
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/* RESET device */
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dm9000_reset(db);
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if (dm9000_probe(db) < 0)
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return -1;
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/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
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io_mode = dm9000_ior(db, DM9000_ISR) >> 6;
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switch (io_mode) {
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case 0x0: /* 16-bit mode */
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printf("DM9000: running in 16 bit mode\n");
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db->outblk = dm9000_outblk_16bit;
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db->inblk = dm9000_inblk_16bit;
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db->rx_status = dm9000_rx_status_16bit;
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break;
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case 0x01: /* 32-bit mode */
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printf("DM9000: running in 32 bit mode\n");
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db->outblk = dm9000_outblk_32bit;
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db->inblk = dm9000_inblk_32bit;
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db->rx_status = dm9000_rx_status_32bit;
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break;
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case 0x02: /* 8 bit mode */
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printf("DM9000: running in 8 bit mode\n");
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db->outblk = dm9000_outblk_8bit;
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db->inblk = dm9000_inblk_8bit;
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db->rx_status = dm9000_rx_status_8bit;
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break;
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default:
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/* Assume 8 bit mode, will probably not work anyway */
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printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
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db->outblk = dm9000_outblk_8bit;
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db->inblk = dm9000_inblk_8bit;
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db->rx_status = dm9000_rx_status_8bit;
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break;
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}
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/* Program operating register, only internal phy supported */
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dm9000_iow(db, DM9000_NCR, 0x0);
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/* TX Polling clear */
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dm9000_iow(db, DM9000_TCR, 0);
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/* Less 3Kb, 200us */
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dm9000_iow(db, DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
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/* Flow Control : High/Low Water */
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dm9000_iow(db, DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
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/* SH FIXME: This looks strange! Flow Control */
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dm9000_iow(db, DM9000_FCR, 0x0);
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/* Special Mode */
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dm9000_iow(db, DM9000_SMCR, 0);
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/* clear TX status */
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dm9000_iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
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/* Clear interrupt status */
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dm9000_iow(db, DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
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printf("MAC: %pM\n", enetaddr);
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if (!is_valid_ethaddr(enetaddr))
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printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
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/* fill device MAC address registers */
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for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
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dm9000_iow(db, oft, enetaddr[i]);
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for (i = 0, oft = 0x16; i < 8; i++, oft++)
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dm9000_iow(db, oft, 0xff);
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/* read back mac, just to be sure */
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for (i = 0, oft = 0x10; i < 6; i++, oft++)
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debug("%02x:", dm9000_ior(db, oft));
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debug("\n");
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/* Activate DM9000 */
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/* RX enable */
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dm9000_iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
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/* Enable TX/RX interrupt mask */
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dm9000_iow(db, DM9000_IMR, IMR_PAR);
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i = 0;
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while (!(dm9000_phy_read(db, 1) & 0x20)) { /* autonegation complete bit */
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udelay(1000);
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i++;
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if (i == 10000) {
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printf("could not establish link\n");
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return 0;
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}
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}
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/* see what we've got */
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lnk = dm9000_phy_read(db, 17) >> 12;
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printf("operating at ");
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switch (lnk) {
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case 1:
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printf("10M half duplex ");
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break;
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case 2:
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printf("10M full duplex ");
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break;
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case 4:
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printf("100M half duplex ");
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break;
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case 8:
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printf("100M full duplex ");
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break;
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default:
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printf("unknown: %d ", lnk);
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break;
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}
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printf("mode\n");
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return 0;
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}
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/*
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* Hardware start transmission.
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* Send a packet to media from the upper layer.
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*/
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static int dm9000_send_common(struct dm9000_priv *db, void *packet, int length)
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{
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int tmo;
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dm9000_dump_packet(__func__, packet, length);
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dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
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/* Move data to DM9000 TX RAM */
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dm9000_outb(DM9000_MWCMD, db->base_io); /* Prepare for TX-data */
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|
|
/* push the data to the TX-fifo */
|
|
db->outblk(db, packet, length);
|
|
|
|
/* Set TX length to DM9000 */
|
|
dm9000_iow(db, DM9000_TXPLL, length & 0xff);
|
|
dm9000_iow(db, DM9000_TXPLH, (length >> 8) & 0xff);
|
|
|
|
/* Issue TX polling command */
|
|
dm9000_iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
|
|
|
|
/* wait for end of transmission */
|
|
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
|
|
while (!(dm9000_ior(db, DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
|
|
!(dm9000_ior(db, DM9000_ISR) & IMR_PTM)) {
|
|
if (get_timer(0) >= tmo) {
|
|
printf("transmission timeout\n");
|
|
break;
|
|
}
|
|
}
|
|
dm9000_iow(db, DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
|
|
|
|
debug("transmit done\n\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Stop the interface.
|
|
* The interface is stopped when it is brought.
|
|
*/
|
|
static void dm9000_halt_common(struct dm9000_priv *db)
|
|
{
|
|
/* RESET device */
|
|
dm9000_phy_write(db, 0, 0x8000); /* PHY RESET */
|
|
dm9000_iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
|
|
dm9000_iow(db, DM9000_IMR, 0x80); /* Disable all interrupt */
|
|
dm9000_iow(db, DM9000_RCR, 0x00); /* Disable RX */
|
|
}
|
|
|
|
/*
|
|
* Received a packet and pass to upper layer
|
|
*/
|
|
static int dm9000_recv_common(struct dm9000_priv *db, uchar *rdptr)
|
|
{
|
|
u8 rxbyte;
|
|
u16 rxstatus, rxlen = 0;
|
|
|
|
/*
|
|
* Check packet ready or not, we must check
|
|
* the ISR status first for DM9000A
|
|
*/
|
|
if (!(dm9000_ior(db, DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
|
|
return 0;
|
|
|
|
dm9000_iow(db, DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
|
|
|
|
/* There is _at least_ 1 package in the fifo, read them all */
|
|
dm9000_ior(db, DM9000_MRCMDX); /* Dummy read */
|
|
|
|
/*
|
|
* Get most updated data,
|
|
* only look at bits 0:1, See application notes DM9000
|
|
*/
|
|
rxbyte = dm9000_inb(db->base_data) & 0x03;
|
|
|
|
/* Status check: this byte must be 0 or 1 */
|
|
if (rxbyte > DM9000_PKT_RDY) {
|
|
dm9000_iow(db, DM9000_RCR, 0x00); /* Stop Device */
|
|
dm9000_iow(db, DM9000_ISR, 0x80); /* Stop INT request */
|
|
printf("DM9000 error: status check fail: 0x%x\n",
|
|
rxbyte);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (rxbyte != DM9000_PKT_RDY)
|
|
return 0; /* No packet received, ignore */
|
|
|
|
debug("receiving packet\n");
|
|
|
|
/* A packet ready now & Get status/length */
|
|
db->rx_status(db, &rxstatus, &rxlen);
|
|
|
|
debug("rx status: 0x%04x rx len: %d\n", rxstatus, rxlen);
|
|
|
|
/* Move data from DM9000 */
|
|
/* Read received packet from RX SRAM */
|
|
db->inblk(db, rdptr, rxlen);
|
|
|
|
if (rxstatus & 0xbf00 || rxlen < 0x40 || rxlen > DM9000_PKT_MAX) {
|
|
if (rxstatus & 0x100)
|
|
printf("rx fifo error\n");
|
|
if (rxstatus & 0x200)
|
|
printf("rx crc error\n");
|
|
if (rxstatus & 0x8000)
|
|
printf("rx length error\n");
|
|
if (rxlen > DM9000_PKT_MAX) {
|
|
printf("rx length too big\n");
|
|
dm9000_reset(db);
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
return rxlen;
|
|
}
|
|
|
|
/*
|
|
* Read a word data from SROM
|
|
*/
|
|
#if !defined(CONFIG_DM9000_NO_SROM)
|
|
static void dm9000_read_srom_word(struct dm9000_priv *db, int offset, u8 *to)
|
|
{
|
|
dm9000_iow(db, DM9000_EPAR, offset);
|
|
dm9000_iow(db, DM9000_EPCR, 0x4);
|
|
mdelay(8);
|
|
dm9000_iow(db, DM9000_EPCR, 0x0);
|
|
to[0] = dm9000_ior(db, DM9000_EPDRL);
|
|
to[1] = dm9000_ior(db, DM9000_EPDRH);
|
|
}
|
|
|
|
static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 3; i++)
|
|
dm9000_read_srom_word(db, i, enetaddr + (2 * i));
|
|
}
|
|
#else
|
|
static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {}
|
|
#endif
|
|
|
|
#ifndef CONFIG_DM_ETH
|
|
static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
|
|
{
|
|
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
|
|
|
|
return dm9000_init_common(db, dev->enetaddr);
|
|
}
|
|
|
|
static void dm9000_halt(struct eth_device *dev)
|
|
{
|
|
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
|
|
|
|
dm9000_halt_common(db);
|
|
}
|
|
|
|
static int dm9000_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
|
|
|
|
return dm9000_send_common(db, packet, length);
|
|
}
|
|
|
|
static int dm9000_recv(struct eth_device *dev)
|
|
{
|
|
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
|
|
int ret;
|
|
|
|
ret = dm9000_recv_common(db, net_rx_packets[0]);
|
|
if (ret > 0)
|
|
net_process_received_packet(net_rx_packets[0], ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int dm9000_initialize(struct bd_info *bis)
|
|
{
|
|
struct dm9000_priv *priv;
|
|
struct eth_device *dev;
|
|
|
|
priv = calloc(1, sizeof(*priv));
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
dev = &priv->dev;
|
|
|
|
priv->base_io = (void __iomem *)DM9000_IO;
|
|
priv->base_data = (void __iomem *)DM9000_DATA;
|
|
|
|
/* Load MAC address from EEPROM */
|
|
dm9000_get_enetaddr(priv, dev->enetaddr);
|
|
|
|
dev->init = dm9000_init;
|
|
dev->halt = dm9000_halt;
|
|
dev->send = dm9000_send;
|
|
dev->recv = dm9000_recv;
|
|
strcpy(dev->name, "dm9000");
|
|
|
|
eth_register(&priv->dev);
|
|
|
|
return 0;
|
|
}
|
|
#else /* ifdef CONFIG_DM_ETH */
|
|
static int dm9000_start(struct udevice *dev)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
return dm9000_init_common(db, pdata->enetaddr);
|
|
}
|
|
|
|
static void dm9000_stop(struct udevice *dev)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
|
|
dm9000_halt_common(db);
|
|
}
|
|
|
|
static int dm9000_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = dm9000_send_common(db, packet, length);
|
|
|
|
return ret ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static int dm9000_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
uchar *data = net_rx_packets[0];
|
|
int ret;
|
|
|
|
ret = dm9000_recv_common(db, data);
|
|
if (ret > 0)
|
|
*packetp = (void *)data;
|
|
|
|
return ret >= 0 ? ret : -EAGAIN;
|
|
}
|
|
|
|
static int dm9000_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
int i, oft;
|
|
|
|
/* fill device MAC address registers */
|
|
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
|
|
dm9000_iow(db, oft, pdata->enetaddr[i]);
|
|
|
|
for (i = 0, oft = 0x16; i < 8; i++, oft++)
|
|
dm9000_iow(db, oft, 0xff);
|
|
|
|
/* read back mac, just to be sure */
|
|
for (i = 0, oft = 0x10; i < 6; i++, oft++)
|
|
debug("%02x:", dm9000_ior(db, oft));
|
|
|
|
debug("\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dm9000_read_rom_hwaddr(struct udevice *dev)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
dm9000_get_enetaddr(db, pdata->enetaddr);
|
|
|
|
return !is_valid_ethaddr(pdata->enetaddr);
|
|
}
|
|
|
|
static int dm9000_bind(struct udevice *dev)
|
|
{
|
|
return device_set_name(dev, dev->name);
|
|
}
|
|
|
|
static int dm9000_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct dm9000_priv *db = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
|
|
pdata->iobase = dev_read_addr_index(dev, 0);
|
|
db->base_io = (void __iomem *)pdata->iobase;
|
|
db->base_data = (void __iomem *)dev_read_addr_index(dev, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops dm9000_ops = {
|
|
.start = dm9000_start,
|
|
.stop = dm9000_stop,
|
|
.send = dm9000_send,
|
|
.recv = dm9000_recv,
|
|
.write_hwaddr = dm9000_write_hwaddr,
|
|
.read_rom_hwaddr = dm9000_read_rom_hwaddr,
|
|
};
|
|
|
|
static const struct udevice_id dm9000_ids[] = {
|
|
{ .compatible = "davicom,dm9000" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(dm9000) = {
|
|
.name = "eth_dm9000",
|
|
.id = UCLASS_ETH,
|
|
.of_match = dm9000_ids,
|
|
.bind = dm9000_bind,
|
|
.of_to_plat = dm9000_of_to_plat,
|
|
.ops = &dm9000_ops,
|
|
.priv_auto = sizeof(struct dm9000_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
#endif
|