mirror of
https://github.com/AsahiLinux/u-boot
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ffb0f6f488
Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make it compatible with Linux' naming. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
1293 lines
32 KiB
C
1293 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Atheros AR71xx / AR9xxx GMAC driver
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*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <net.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <linux/bitops.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mii.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <mach/ath79.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum ag7xxx_model {
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AG7XXX_MODEL_AG933X,
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AG7XXX_MODEL_AG934X,
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AG7XXX_MODEL_AG953X,
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AG7XXX_MODEL_AG956X
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};
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/* MAC Configuration 1 */
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#define AG7XXX_ETH_CFG1 0x00
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#define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
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#define AG7XXX_ETH_CFG1_RX_RST BIT(19)
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#define AG7XXX_ETH_CFG1_TX_RST BIT(18)
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#define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
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#define AG7XXX_ETH_CFG1_RX_EN BIT(2)
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#define AG7XXX_ETH_CFG1_TX_EN BIT(0)
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/* MAC Configuration 2 */
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#define AG7XXX_ETH_CFG2 0x04
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#define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
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#define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
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#define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
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#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
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#define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
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#define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
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#define AG7XXX_ETH_CFG2_FDX BIT(0)
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/* MII Configuration */
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#define AG7XXX_ETH_MII_MGMT_CFG 0x20
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#define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
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/* MII Command */
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#define AG7XXX_ETH_MII_MGMT_CMD 0x24
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#define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
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/* MII Address */
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#define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
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#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
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/* MII Control */
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#define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
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/* MII Status */
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#define AG7XXX_ETH_MII_MGMT_STATUS 0x30
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/* MII Indicators */
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#define AG7XXX_ETH_MII_MGMT_IND 0x34
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#define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
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#define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
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/* STA Address 1 & 2 */
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#define AG7XXX_ETH_ADDR1 0x40
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#define AG7XXX_ETH_ADDR2 0x44
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/* ETH Configuration 0 - 5 */
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#define AG7XXX_ETH_FIFO_CFG_0 0x48
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#define AG7XXX_ETH_FIFO_CFG_1 0x4c
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#define AG7XXX_ETH_FIFO_CFG_2 0x50
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#define AG7XXX_ETH_FIFO_CFG_3 0x54
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#define AG7XXX_ETH_FIFO_CFG_4 0x58
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#define AG7XXX_ETH_FIFO_CFG_5 0x5c
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/* DMA Transfer Control for Queue 0 */
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#define AG7XXX_ETH_DMA_TX_CTRL 0x180
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#define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
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/* Descriptor Address for Queue 0 Tx */
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#define AG7XXX_ETH_DMA_TX_DESC 0x184
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/* DMA Tx Status */
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#define AG7XXX_ETH_DMA_TX_STATUS 0x188
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/* Rx Control */
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#define AG7XXX_ETH_DMA_RX_CTRL 0x18c
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#define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
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/* Pointer to Rx Descriptor */
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#define AG7XXX_ETH_DMA_RX_DESC 0x190
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/* Rx Status */
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#define AG7XXX_ETH_DMA_RX_STATUS 0x194
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/* Custom register at 0x1805002C */
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#define AG7XXX_ETH_XMII 0x2C
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#define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
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#define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
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#define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
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#define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
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(((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
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#define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
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#define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
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#define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
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(((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
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#define AG7XXX_ETH_XMII_GIGE BIT(25)
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/* Custom register at 0x18070000 */
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#define AG7XXX_GMAC_ETH_CFG 0x00
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#define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
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#define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
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#define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
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(((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
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#define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
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#define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
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#define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
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(((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
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#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
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#define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
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#define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
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#define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
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#define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
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#define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
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#define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
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#define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
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#define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
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#define CONFIG_TX_DESCR_NUM 8
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#define CONFIG_RX_DESCR_NUM 8
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#define CONFIG_ETH_BUFSIZE 2048
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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/* DMA descriptor. */
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struct ag7xxx_dma_desc {
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u32 data_addr;
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#define AG7XXX_DMADESC_IS_EMPTY BIT(31)
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#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
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#define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
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#define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
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u32 config;
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u32 next_desc;
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u32 _pad[5];
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};
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struct ar7xxx_eth_priv {
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struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
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struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
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char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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void __iomem *regs;
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void __iomem *phyregs;
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struct eth_device *dev;
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struct phy_device *phydev;
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struct mii_dev *bus;
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u32 interface;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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enum ag7xxx_model model;
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};
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/*
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* Switch and MDIO access
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*/
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static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
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{
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struct ar7xxx_eth_priv *priv = bus->priv;
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void __iomem *regs = priv->phyregs;
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int ret;
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writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
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writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
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regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
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writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
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regs + AG7XXX_ETH_MII_MGMT_CMD);
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ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
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AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
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if (ret)
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return ret;
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*val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
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writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
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return 0;
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}
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static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
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{
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struct ar7xxx_eth_priv *priv = bus->priv;
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void __iomem *regs = priv->phyregs;
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int ret;
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writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
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regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
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writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
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ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
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AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
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return ret;
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}
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static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
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{
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struct ar7xxx_eth_priv *priv = bus->priv;
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u32 phy_addr;
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u32 reg_addr;
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u32 phy_temp;
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u32 reg_temp;
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u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
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u16 rv = 0;
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int ret;
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if (priv->model == AG7XXX_MODEL_AG933X ||
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priv->model == AG7XXX_MODEL_AG953X) {
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phy_addr = 0x1f;
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reg_addr = 0x10;
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} else if (priv->model == AG7XXX_MODEL_AG934X ||
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priv->model == AG7XXX_MODEL_AG956X) {
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phy_addr = 0x18;
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reg_addr = 0x00;
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} else
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return -EINVAL;
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if (priv->model == AG7XXX_MODEL_AG956X)
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ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
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else
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ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
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if (ret)
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return ret;
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phy_temp = ((reg >> 6) & 0x7) | 0x10;
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if (priv->model == AG7XXX_MODEL_AG956X)
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reg_temp = reg_temp_w & 0x1f;
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else
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reg_temp = (reg >> 1) & 0x1e;
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*val = 0;
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ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
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if (ret < 0)
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return ret;
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*val |= rv;
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if (priv->model == AG7XXX_MODEL_AG956X) {
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phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
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reg_temp = (reg_temp_w + 1) & 0x1f;
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ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
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} else {
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ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
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}
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if (ret < 0)
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return ret;
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*val |= (rv << 16);
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return 0;
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}
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static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
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{
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struct ar7xxx_eth_priv *priv = bus->priv;
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u32 phy_addr;
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u32 reg_addr;
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u32 phy_temp;
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u32 reg_temp;
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u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
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int ret;
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if (priv->model == AG7XXX_MODEL_AG933X ||
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priv->model == AG7XXX_MODEL_AG953X) {
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phy_addr = 0x1f;
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reg_addr = 0x10;
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} else if (priv->model == AG7XXX_MODEL_AG934X ||
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priv->model == AG7XXX_MODEL_AG956X) {
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phy_addr = 0x18;
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reg_addr = 0x00;
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} else
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return -EINVAL;
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if (priv->model == AG7XXX_MODEL_AG956X)
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ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
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else
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ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
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if (ret)
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return ret;
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if (priv->model == AG7XXX_MODEL_AG956X) {
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reg_temp = (reg_temp_w + 1) & 0x1f;
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phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
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} else {
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phy_temp = ((reg >> 6) & 0x7) | 0x10;
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reg_temp = (reg >> 1) & 0x1e;
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}
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/*
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* The switch on AR933x has some special register behavior, which
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* expects particular write order of their nibbles:
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* 0x40 ..... MSB first, LSB second
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* 0x50 ..... MSB first, LSB second
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* 0x98 ..... LSB first, MSB second
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* others ... don't care
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*/
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if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
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ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
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if (ret < 0)
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return ret;
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ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
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if (ret < 0)
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return ret;
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} else {
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if (priv->model == AG7XXX_MODEL_AG956X)
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ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
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else
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ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
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if (ret < 0)
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return ret;
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if (priv->model == AG7XXX_MODEL_AG956X) {
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phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
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reg_temp = reg_temp_w & 0x1f;
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}
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ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
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{
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u32 data;
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unsigned long start;
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int ret;
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/* No idea if this is long enough or too long */
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int timeout_ms = 1000;
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/* Dummy read followed by PHY read/write command. */
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ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
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if (ret < 0)
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return ret;
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data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
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ret = ag7xxx_switch_reg_write(bus, 0x98, data);
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if (ret < 0)
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return ret;
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start = get_timer(0);
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/* Wait for operation to finish */
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do {
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ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
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if (ret < 0)
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return ret;
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if (get_timer(start) > timeout_ms)
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return -ETIMEDOUT;
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} while (data & BIT(31));
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return data & 0xffff;
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}
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static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
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}
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static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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int ret;
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ret = ag7xxx_mdio_rw(bus, addr, reg, val);
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if (ret < 0)
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return ret;
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return 0;
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}
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/*
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* DMA ring handlers
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*/
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static void ag7xxx_dma_clean_tx(struct udevice *dev)
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{
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struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
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struct ag7xxx_dma_desc *curr, *next;
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u32 start, end;
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int i;
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for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
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curr = &priv->tx_mac_descrtable[i];
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next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
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curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
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curr->config = AG7XXX_DMADESC_IS_EMPTY;
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curr->next_desc = virt_to_phys(next);
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}
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priv->tx_currdescnum = 0;
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/* Cache: Flush descriptors, don't care about buffers. */
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start = (u32)(&priv->tx_mac_descrtable[0]);
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end = start + sizeof(priv->tx_mac_descrtable);
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flush_dcache_range(start, end);
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}
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static void ag7xxx_dma_clean_rx(struct udevice *dev)
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{
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struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
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struct ag7xxx_dma_desc *curr, *next;
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u32 start, end;
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int i;
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for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
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curr = &priv->rx_mac_descrtable[i];
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next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
|
|
|
|
curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
|
|
curr->config = AG7XXX_DMADESC_IS_EMPTY;
|
|
curr->next_desc = virt_to_phys(next);
|
|
}
|
|
|
|
priv->rx_currdescnum = 0;
|
|
|
|
/* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
|
|
start = (u32)(&priv->rx_mac_descrtable[0]);
|
|
end = start + sizeof(priv->rx_mac_descrtable);
|
|
flush_dcache_range(start, end);
|
|
invalidate_dcache_range(start, end);
|
|
|
|
start = (u32)&priv->rxbuffs;
|
|
end = start + sizeof(priv->rxbuffs);
|
|
invalidate_dcache_range(start, end);
|
|
}
|
|
|
|
/*
|
|
* Ethernet I/O
|
|
*/
|
|
static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
struct ag7xxx_dma_desc *curr;
|
|
u32 start, end;
|
|
|
|
curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
|
|
|
|
/* Cache: Invalidate descriptor. */
|
|
start = (u32)curr;
|
|
end = start + sizeof(*curr);
|
|
invalidate_dcache_range(start, end);
|
|
|
|
if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
|
|
printf("ag7xxx: Out of TX DMA descriptors!\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
/* Copy the packet into the data buffer. */
|
|
memcpy(phys_to_virt(curr->data_addr), packet, length);
|
|
curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
|
|
|
|
/* Cache: Flush descriptor, Flush buffer. */
|
|
start = (u32)curr;
|
|
end = start + sizeof(*curr);
|
|
flush_dcache_range(start, end);
|
|
start = (u32)phys_to_virt(curr->data_addr);
|
|
end = start + length;
|
|
flush_dcache_range(start, end);
|
|
|
|
/* Load the DMA descriptor and start TX DMA. */
|
|
writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
|
|
priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
|
|
|
|
/* Switch to next TX descriptor. */
|
|
priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
struct ag7xxx_dma_desc *curr;
|
|
u32 start, end, length;
|
|
|
|
curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
|
|
|
|
/* Cache: Invalidate descriptor. */
|
|
start = (u32)curr;
|
|
end = start + sizeof(*curr);
|
|
invalidate_dcache_range(start, end);
|
|
|
|
/* No packets received. */
|
|
if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
|
|
return -EAGAIN;
|
|
|
|
length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
|
|
|
|
/* Cache: Invalidate buffer. */
|
|
start = (u32)phys_to_virt(curr->data_addr);
|
|
end = start + length;
|
|
invalidate_dcache_range(start, end);
|
|
|
|
/* Receive one packet and return length. */
|
|
*packetp = phys_to_virt(curr->data_addr);
|
|
return length;
|
|
}
|
|
|
|
static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
|
|
int length)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
struct ag7xxx_dma_desc *curr;
|
|
u32 start, end;
|
|
|
|
curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
|
|
|
|
curr->config = AG7XXX_DMADESC_IS_EMPTY;
|
|
|
|
/* Cache: Flush descriptor. */
|
|
start = (u32)curr;
|
|
end = start + sizeof(*curr);
|
|
flush_dcache_range(start, end);
|
|
|
|
/* Switch to next RX descriptor. */
|
|
priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag7xxx_eth_start(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
/* FIXME: Check if link up */
|
|
|
|
/* Clear the DMA rings. */
|
|
ag7xxx_dma_clean_tx(dev);
|
|
ag7xxx_dma_clean_rx(dev);
|
|
|
|
/* Load DMA descriptors and start the RX DMA. */
|
|
writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
|
|
priv->regs + AG7XXX_ETH_DMA_TX_DESC);
|
|
writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
|
|
priv->regs + AG7XXX_ETH_DMA_RX_DESC);
|
|
writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
|
|
priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ag7xxx_eth_stop(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
/* Stop the TX DMA. */
|
|
writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
|
|
wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
|
|
1000, 0);
|
|
|
|
/* Stop the RX DMA. */
|
|
writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
|
|
wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
|
|
1000, 0);
|
|
}
|
|
|
|
/*
|
|
* Hardware setup
|
|
*/
|
|
static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
unsigned char *mac = pdata->enetaddr;
|
|
u32 macid_lo, macid_hi;
|
|
|
|
macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
|
|
macid_lo = (mac[5] << 16) | (mac[4] << 24);
|
|
|
|
writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
|
|
writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ag7xxx_hw_setup(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
u32 speed;
|
|
|
|
setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
|
|
AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
|
|
AG7XXX_ETH_CFG1_SOFT_RST);
|
|
|
|
mdelay(10);
|
|
|
|
writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
|
|
priv->regs + AG7XXX_ETH_CFG1);
|
|
|
|
if (priv->interface == PHY_INTERFACE_MODE_RMII)
|
|
speed = AG7XXX_ETH_CFG2_IF_10_100;
|
|
else
|
|
speed = AG7XXX_ETH_CFG2_IF_1000;
|
|
|
|
clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
|
|
AG7XXX_ETH_CFG2_IF_SPEED_MASK,
|
|
speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
|
|
AG7XXX_ETH_CFG2_LEN_CHECK);
|
|
|
|
writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
|
|
writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
|
|
|
|
writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
|
|
setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
|
|
writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
|
|
writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
|
|
writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
|
|
writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
|
|
}
|
|
|
|
static int ag7xxx_mii_get_div(void)
|
|
{
|
|
ulong freq = get_bus_freq(0);
|
|
|
|
switch (freq / 1000000) {
|
|
case 150: return 0x7;
|
|
case 175: return 0x5;
|
|
case 200: return 0x4;
|
|
case 210: return 0x9;
|
|
case 220: return 0x9;
|
|
default: return 0x7;
|
|
}
|
|
}
|
|
|
|
static int ag7xxx_mii_setup(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret, div = ag7xxx_mii_get_div();
|
|
u32 reg;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG933X) {
|
|
/* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
|
|
if (priv->interface == PHY_INTERFACE_MODE_RMII)
|
|
return 0;
|
|
}
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG934X)
|
|
reg = 0x4;
|
|
else if (priv->model == AG7XXX_MODEL_AG953X)
|
|
reg = 0x2;
|
|
else if (priv->model == AG7XXX_MODEL_AG956X)
|
|
reg = 0x7;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG934X ||
|
|
priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X) {
|
|
writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
|
|
priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
|
|
writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
|
|
priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
|
|
writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
|
|
|
|
/* Check the switch */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®);
|
|
if (ret)
|
|
continue;
|
|
|
|
if (reg != 0x18007fff)
|
|
continue;
|
|
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int ag933x_phy_setup_wan(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
/* Configure switch port 4 (GMAC0) */
|
|
return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
|
|
}
|
|
|
|
static int ag933x_phy_setup_lan(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret;
|
|
u32 reg;
|
|
|
|
/* Reset the switch */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
reg |= BIT(31);
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
do {
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
} while (reg & BIT(31));
|
|
|
|
/* Configure switch ports 0...3 (GMAC1) */
|
|
for (i = 0; i < 4; i++) {
|
|
ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* Enable CPU port */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* QM Control */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Disable Atheros header */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Tag priority mapping */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable ARP packets to the CPU */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
|
|
if (ret)
|
|
return ret;
|
|
reg |= 0x100000;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag953x_phy_setup_wan(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
u32 reg = 0;
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
/* Set wan port connect to GE0 */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x8, ®);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Configure switch port 4 (GMAC0) */
|
|
ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag953x_phy_setup_lan(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret;
|
|
u32 reg = 0;
|
|
|
|
/* Reset the switch */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
|
|
if (ret)
|
|
return ret;
|
|
|
|
do {
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
} while (reg & BIT(31));
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Set GMII mode */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x4, ®);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Configure switch ports 0...4 (GMAC1) */
|
|
for (i = 0; i < 5; i++) {
|
|
ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* QM Control */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Disable Atheros header */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Tag priority mapping */
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable ARP packets to the CPU */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable broadcast packets to the CPU */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, ®);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X) {
|
|
ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
|
|
ADVERTISE_ALL);
|
|
} else {
|
|
ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
|
|
ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
|
|
ADVERTISE_PAUSE_ASYM);
|
|
}
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG934X) {
|
|
ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
|
|
ADVERTISE_1000FULL);
|
|
if (ret)
|
|
return ret;
|
|
} else if (priv->model == AG7XXX_MODEL_AG956X) {
|
|
ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
|
|
ADVERTISE_1000FULL);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X)
|
|
return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
|
|
BMCR_ANENABLE | BMCR_RESET);
|
|
|
|
return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
|
|
BMCR_ANENABLE | BMCR_RESET);
|
|
}
|
|
|
|
static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
u16 reg;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X) {
|
|
do {
|
|
ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, ®);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
} while (reg & BMCR_RESET);
|
|
} else {
|
|
do {
|
|
ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
|
|
if (ret < 0)
|
|
return ret;
|
|
mdelay(10);
|
|
} while (ret & BMCR_RESET);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag933x_phy_setup_common(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret, phymax;
|
|
u16 reg;
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG933X)
|
|
phymax = 4;
|
|
else if (priv->model == AG7XXX_MODEL_AG934X ||
|
|
priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X)
|
|
phymax = 5;
|
|
else
|
|
return -EINVAL;
|
|
|
|
if (priv->interface == PHY_INTERFACE_MODE_RMII) {
|
|
ret = ag933x_phy_setup_reset_set(dev, phymax);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag933x_phy_setup_reset_fin(dev, phymax);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Read out link status */
|
|
if (priv->model == AG7XXX_MODEL_AG953X)
|
|
ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, ®);
|
|
else
|
|
ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Switch ports */
|
|
for (i = 0; i < phymax; i++) {
|
|
ret = ag933x_phy_setup_reset_set(dev, i);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < phymax; i++) {
|
|
ret = ag933x_phy_setup_reset_fin(dev, i);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < phymax; i++) {
|
|
/* Read out link status */
|
|
if (priv->model == AG7XXX_MODEL_AG953X ||
|
|
priv->model == AG7XXX_MODEL_AG956X)
|
|
ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, ®);
|
|
else
|
|
ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag934x_phy_setup(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret;
|
|
u32 reg;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* AR8327/AR8328 v1.0 fixup */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
if ((reg & 0xffff) == 0x1201) {
|
|
for (i = 0; i < 5; i++) {
|
|
ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®);
|
|
if (ret)
|
|
return ret;
|
|
reg &= ~0x70000;
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag956x_phy_setup(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int i, ret;
|
|
u32 reg, ctrl;
|
|
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0x0, ®);
|
|
if (ret)
|
|
return ret;
|
|
if ((reg & 0xffff) >= 0x1301)
|
|
ctrl = 0xc74164de;
|
|
else
|
|
ctrl = 0xc74164d0;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Values suggested by the switch team when s17 in sgmii
|
|
* configuration. 0x10(S17_PWS_REG) = 0x602613a0
|
|
*/
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* AR8337/AR8334 v1.0 fixup */
|
|
ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
|
|
if (ret)
|
|
return ret;
|
|
if ((reg & 0xffff) == 0x1301) {
|
|
for (i = 0; i < 5; i++) {
|
|
/* Turn on Gigabit clock */
|
|
ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
|
|
if (ret)
|
|
return ret;
|
|
ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ag7xxx_mac_probe(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ag7xxx_hw_setup(dev);
|
|
ret = ag7xxx_mii_setup(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ag7xxx_eth_write_hwaddr(dev);
|
|
|
|
if (priv->model == AG7XXX_MODEL_AG933X) {
|
|
if (priv->interface == PHY_INTERFACE_MODE_RMII)
|
|
ret = ag933x_phy_setup_wan(dev);
|
|
else
|
|
ret = ag933x_phy_setup_lan(dev);
|
|
} else if (priv->model == AG7XXX_MODEL_AG953X) {
|
|
if (priv->interface == PHY_INTERFACE_MODE_RMII)
|
|
ret = ag953x_phy_setup_wan(dev);
|
|
else
|
|
ret = ag953x_phy_setup_lan(dev);
|
|
} else if (priv->model == AG7XXX_MODEL_AG934X) {
|
|
ret = ag934x_phy_setup(dev);
|
|
} else if (priv->model == AG7XXX_MODEL_AG956X) {
|
|
ret = ag956x_phy_setup(dev);
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
return ag933x_phy_setup_common(dev);
|
|
}
|
|
|
|
static int ag7xxx_mdio_probe(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
struct mii_dev *bus = mdio_alloc();
|
|
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
|
|
bus->read = ag7xxx_mdio_read;
|
|
bus->write = ag7xxx_mdio_write;
|
|
snprintf(bus->name, sizeof(bus->name), dev->name);
|
|
|
|
bus->priv = (void *)priv;
|
|
|
|
return mdio_register(bus);
|
|
}
|
|
|
|
static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
|
|
{
|
|
int offset;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
|
|
if (offset <= 0) {
|
|
debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
|
|
return -EINVAL;
|
|
}
|
|
|
|
offset = fdt_parent_offset(gd->fdt_blob, offset);
|
|
if (offset <= 0) {
|
|
debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
|
|
__func__, offset);
|
|
return -EINVAL;
|
|
}
|
|
|
|
offset = fdt_parent_offset(gd->fdt_blob, offset);
|
|
if (offset <= 0) {
|
|
debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
|
|
__func__, offset);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return offset;
|
|
}
|
|
|
|
static int ag7xxx_eth_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
void __iomem *iobase, *phyiobase;
|
|
int ret, phyreg;
|
|
|
|
/* Decoding of convoluted PHY wiring on Atheros MIPS. */
|
|
ret = ag7xxx_get_phy_iface_offset(dev);
|
|
if (ret <= 0)
|
|
return ret;
|
|
phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
|
|
|
|
iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
|
|
phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
|
|
|
|
debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
|
|
__func__, iobase, phyiobase, priv);
|
|
priv->regs = iobase;
|
|
priv->phyregs = phyiobase;
|
|
priv->interface = pdata->phy_interface;
|
|
priv->model = dev_get_driver_data(dev);
|
|
|
|
ret = ag7xxx_mdio_probe(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
ret = ag7xxx_mac_probe(dev);
|
|
debug("%s, ret=%d\n", __func__, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ag7xxx_eth_remove(struct udevice *dev)
|
|
{
|
|
struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops ag7xxx_eth_ops = {
|
|
.start = ag7xxx_eth_start,
|
|
.send = ag7xxx_eth_send,
|
|
.recv = ag7xxx_eth_recv,
|
|
.free_pkt = ag7xxx_eth_free_pkt,
|
|
.stop = ag7xxx_eth_stop,
|
|
.write_hwaddr = ag7xxx_eth_write_hwaddr,
|
|
};
|
|
|
|
static int ag7xxx_eth_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_plat(dev);
|
|
int ret;
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
pdata->phy_interface = -1;
|
|
|
|
/* Decoding of convoluted PHY wiring on Atheros MIPS. */
|
|
ret = ag7xxx_get_phy_iface_offset(dev);
|
|
if (ret <= 0)
|
|
return ret;
|
|
|
|
pdata->phy_interface = dev_read_phy_mode(dev);
|
|
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id ag7xxx_eth_ids[] = {
|
|
{ .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
|
|
{ .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
|
|
{ .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
|
|
{ .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_ag7xxx) = {
|
|
.name = "eth_ag7xxx",
|
|
.id = UCLASS_ETH,
|
|
.of_match = ag7xxx_eth_ids,
|
|
.of_to_plat = ag7xxx_eth_of_to_plat,
|
|
.probe = ag7xxx_eth_probe,
|
|
.remove = ag7xxx_eth_remove,
|
|
.ops = &ag7xxx_eth_ops,
|
|
.priv_auto = sizeof(struct ar7xxx_eth_priv),
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|