mirror of
https://github.com/AsahiLinux/u-boot
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f5bfe15750
Currently, clock/reset setup for this device is handled by a platform-specific function and is intermixed with non-DM pinctrl setup. Use the devicetree to get clocks/resets, which disentagles it from the pinctrl setup in preparation for moving to DM_PINCTRL. This also has the added benefit of picking the right clock/reset bits for H6 and new SoCs that have a rearranged PRCM MMIO space. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
286 lines
7 KiB
C
286 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on allwinner u-boot sources rsb code which is:
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* lixiang <lixiang@allwinnertech.com>
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*/
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#include <axp_pmic.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <reset.h>
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#include <time.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/rsb.h>
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static int sun8i_rsb_await_trans(struct sunxi_rsb_reg *base)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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u32 stat;
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int ret;
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while (1) {
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stat = readl(&base->stat);
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if (stat & RSB_STAT_LBSY_INT) {
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ret = -EBUSY;
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break;
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}
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if (stat & RSB_STAT_TERR_INT) {
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ret = -EIO;
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break;
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}
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if (stat & RSB_STAT_TOVER_INT) {
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ret = 0;
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break;
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}
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if (timer_get_us() > tmo) {
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ret = -ETIME;
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break;
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}
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}
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writel(stat, &base->stat); /* Clear status bits */
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return ret;
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}
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static int sun8i_rsb_do_trans(struct sunxi_rsb_reg *base)
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{
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setbits_le32(&base->ctrl, RSB_CTRL_START_TRANS);
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return sun8i_rsb_await_trans(base);
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}
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static int sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr,
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u8 reg_addr, u8 *data)
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{
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int ret;
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writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
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writel(reg_addr, &base->addr);
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writel(RSB_CMD_BYTE_READ, &base->cmd);
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ret = sun8i_rsb_do_trans(base);
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if (ret)
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return ret;
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*data = readl(&base->data) & 0xff;
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return 0;
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}
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static int sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr,
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u8 reg_addr, u8 data)
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{
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writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr), &base->devaddr);
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writel(reg_addr, &base->addr);
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writel(data, &base->data);
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writel(RSB_CMD_BYTE_WRITE, &base->cmd);
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return sun8i_rsb_do_trans(base);
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}
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static int sun8i_rsb_set_device_address(struct sunxi_rsb_reg *base,
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u16 device_addr, u16 runtime_addr)
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{
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writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
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RSB_DEVADDR_DEVICE_ADDR(device_addr), &base->devaddr);
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writel(RSB_CMD_SET_RTSADDR, &base->cmd);
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return sun8i_rsb_do_trans(base);
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}
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static void sun8i_rsb_set_clk(struct sunxi_rsb_reg *base)
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{
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u32 div = 0;
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u32 cd_odly = 0;
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/* Source is Hosc24M, set RSB clk to 3Mhz */
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div = 24000000 / 3000000 / 2 - 1;
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cd_odly = div >> 1;
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if (!cd_odly)
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cd_odly = 1;
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writel((cd_odly << 8) | div, &base->ccr);
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}
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static int sun8i_rsb_set_device_mode(struct sunxi_rsb_reg *base)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
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&base->dmcr);
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while (readl(&base->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
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if (timer_get_us() > tmo)
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return -ETIME;
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}
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return sun8i_rsb_await_trans(base);
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}
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static int sun8i_rsb_init(struct sunxi_rsb_reg *base)
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{
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writel(RSB_CTRL_SOFT_RST, &base->ctrl);
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sun8i_rsb_set_clk(base);
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return sun8i_rsb_set_device_mode(base);
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}
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#if IS_ENABLED(CONFIG_AXP_PMIC_BUS)
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int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data)
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{
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struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
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return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
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}
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int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data)
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{
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struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
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return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
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}
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int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
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{
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struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
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return sun8i_rsb_set_device_address(base, device_addr, runtime_addr);
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}
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int rsb_init(void)
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{
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struct sunxi_rsb_reg *base = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
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/* Enable RSB and PIO clk, and de-assert their resets */
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prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
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if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
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sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
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sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
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sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
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sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
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sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
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sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
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} else {
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sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
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sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
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sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
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sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
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sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
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sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
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}
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return sun8i_rsb_init(base);
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}
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#endif
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct sun8i_rsb_priv {
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struct sunxi_rsb_reg *base;
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};
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/*
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* The mapping from hardware address to runtime address is fixed, and shared
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* among all RSB drivers. See the comment in drivers/bus/sunxi-rsb.c in Linux.
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*/
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static int sun8i_rsb_get_runtime_address(u16 device_addr)
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{
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if (device_addr == AXP_PMIC_PRI_DEVICE_ADDR)
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return AXP_PMIC_PRI_RUNTIME_ADDR;
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if (device_addr == AXP_PMIC_SEC_DEVICE_ADDR)
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return AXP_PMIC_SEC_RUNTIME_ADDR;
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return -ENXIO;
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}
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static int sun8i_rsb_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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int runtime_addr = sun8i_rsb_get_runtime_address(msg->addr);
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struct sun8i_rsb_priv *priv = dev_get_priv(bus);
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if (runtime_addr < 0)
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return runtime_addr;
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/* The hardware only supports SMBus-style transfers. */
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if (nmsgs == 2 && msg[1].flags == I2C_M_RD && msg[1].len == 1)
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return sun8i_rsb_read(priv->base, runtime_addr,
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msg[0].buf[0], &msg[1].buf[0]);
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if (nmsgs == 1 && msg[0].len == 2)
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return sun8i_rsb_write(priv->base, runtime_addr,
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msg[0].buf[0], msg[0].buf[1]);
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return -EINVAL;
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}
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static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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int runtime_addr = sun8i_rsb_get_runtime_address(chip_addr);
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struct sun8i_rsb_priv *priv = dev_get_priv(bus);
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if (runtime_addr < 0)
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return runtime_addr;
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return sun8i_rsb_set_device_address(priv->base, chip_addr, runtime_addr);
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}
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static int sun8i_rsb_probe(struct udevice *bus)
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{
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struct sun8i_rsb_priv *priv = dev_get_priv(bus);
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struct reset_ctl *reset;
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struct clk *clk;
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priv->base = dev_read_addr_ptr(bus);
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reset = devm_reset_control_get(bus, NULL);
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if (!IS_ERR(reset))
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reset_deassert(reset);
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clk = devm_clk_get(bus, NULL);
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if (!IS_ERR(clk))
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clk_enable(clk);
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return sun8i_rsb_init(priv->base);
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}
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static int sun8i_rsb_child_pre_probe(struct udevice *child)
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{
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struct dm_i2c_chip *chip = dev_get_parent_plat(child);
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struct udevice *bus = child->parent;
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/* Ensure each transfer is for a single register. */
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chip->flags |= DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS;
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return sun8i_rsb_probe_chip(bus, chip->chip_addr, 0);
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}
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static const struct dm_i2c_ops sun8i_rsb_ops = {
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.xfer = sun8i_rsb_xfer,
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.probe_chip = sun8i_rsb_probe_chip,
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};
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static const struct udevice_id sun8i_rsb_ids[] = {
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{ .compatible = "allwinner,sun8i-a23-rsb" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sun8i_rsb) = {
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.name = "sun8i_rsb",
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.id = UCLASS_I2C,
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.of_match = sun8i_rsb_ids,
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.probe = sun8i_rsb_probe,
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.child_pre_probe = sun8i_rsb_child_pre_probe,
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.priv_auto = sizeof(struct sun8i_rsb_priv),
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.ops = &sun8i_rsb_ops,
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};
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#endif /* CONFIG_IS_ENABLED(DM_I2C) */
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