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https://github.com/AsahiLinux/u-boot
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a6cc0b082f
s/actucal/actual/g Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
312 lines
7.3 KiB
C
312 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SMBus block read/write support added by Stefan Roese:
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <pci.h>
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#include <asm/io.h>
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/* PCI Configuration Space (D31:F3): SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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#define HST_EN (1 << 0)
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#define SMB_RCV_SLVA 0x09
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/* SMBus I/O bits. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMBAUXCTL 0xd
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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/* I801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE 0x80
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#define SMBHSTSTS_INUSE_STS 0x40
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#define SMBHSTSTS_SMBALERT_STS 0x20
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#define SMBHSTSTS_FAILED 0x10
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#define SMBHSTSTS_BUS_ERR 0x08
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#define SMBHSTSTS_DEV_ERR 0x04
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#define SMBHSTSTS_INTR 0x02
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#define SMBHSTSTS_HOST_BUSY 0x01
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/* I801 Host Control register bits */
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#define SMBHSTCNT_INTREN 0x01
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#define SMBHSTCNT_KILL 0x02
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#define SMBHSTCNT_LAST_BYTE 0x20
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#define SMBHSTCNT_START 0x40
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#define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
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/* Auxiliary control register bits, ICH4+ only */
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#define SMBAUXCTL_CRC 1
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#define SMBAUXCTL_E32B 2
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#define SMBUS_TIMEOUT 100 /* 100 ms */
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struct intel_i2c {
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u32 base;
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int running;
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};
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static int smbus_wait_until_ready(u32 base)
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{
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unsigned long ts;
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u8 byte;
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ts = get_timer(0);
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do {
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byte = inb(base + SMBHSTSTAT);
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if (!(byte & 1))
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return 0;
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} while (get_timer(ts) < SMBUS_TIMEOUT);
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return -ETIMEDOUT;
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}
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static int smbus_wait_until_done(u32 base)
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{
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unsigned long ts;
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u8 byte;
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ts = get_timer(0);
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do {
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byte = inb(base + SMBHSTSTAT);
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if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
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return 0;
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} while (get_timer(ts) < SMBUS_TIMEOUT);
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return -ETIMEDOUT;
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}
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static int smbus_block_read(u32 base, u8 dev, u8 *buffer,
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int offset, int len)
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{
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u8 buf_temp[32];
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int count;
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int i;
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debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
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__func__, __LINE__, dev, offset, len);
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if (smbus_wait_until_ready(base) < 0)
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return -ETIMEDOUT;
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/* Setup transaction */
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/* Reset the data buffer index */
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inb(base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD);
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/* Set the command/address... */
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outb(offset & 0xff, base + SMBHSTCMD);
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/* Set up for a block read */
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outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
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(base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
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/* Start the command */
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outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(base) < 0) {
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printf("SMBUS read transaction timeout (dev=0x%x)\n", dev);
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return -ETIMEDOUT;
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}
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count = inb(base + SMBHSTDAT0);
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debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len);
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if (count == 0) {
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debug("ERROR: len=0 on read\n");
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return -EIO;
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}
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if (count < len) {
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debug("ERROR: too few bytes read\n");
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return -EIO;
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}
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if (count > 32) {
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debug("ERROR: count=%d too high\n", count);
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return -EIO;
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}
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/* Read all available bytes from buffer */
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for (i = 0; i < count; i++)
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buf_temp[i] = inb(base + SMBBLKDAT);
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memcpy(buffer, buf_temp, len);
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/* Return results of transaction */
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if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
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return -EIO;
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return 0;
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}
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static int smbus_block_write(u32 base, u8 dev, u8 *buffer,
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int offset, int len)
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{
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int i;
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debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
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__func__, __LINE__, dev, offset, len);
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if (smbus_wait_until_ready(base) < 0)
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return -ETIMEDOUT;
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/* Setup transaction */
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/* Set the device I'm talking too */
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outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD);
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/* Set the command/address... */
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outb(offset, base + SMBHSTCMD);
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/* Set up for a block write */
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outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
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(base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
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/* Write count in DAT0 register */
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outb(len, base + SMBHSTDAT0);
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/* Write data bytes... */
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for (i = 0; i < len; i++)
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outb(*buffer++, base + SMBBLKDAT);
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/* Start the command */
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outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(base) < 0) {
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printf("SMBUS write transaction timeout (dev=0x%x)\n", dev);
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return -ETIMEDOUT;
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}
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/* Return results of transaction */
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if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
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return -EIO;
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return 0;
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}
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static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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struct intel_i2c *i2c = dev_get_priv(bus);
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struct i2c_msg *dmsg, *omsg, dummy;
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debug("i2c_xfer: %d messages\n", nmsgs);
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memset(&dummy, 0, sizeof(struct i2c_msg));
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/*
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* We expect either two messages (one with an offset and one with the
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* actual data) or one message (just data)
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*/
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if (nmsgs > 2 || nmsgs == 0) {
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debug("%s: Only one or two messages are supported", __func__);
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return -EIO;
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}
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omsg = nmsgs == 1 ? &dummy : msg;
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dmsg = nmsgs == 1 ? msg : msg + 1;
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if (dmsg->flags & I2C_M_RD)
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return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0],
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omsg->buf[0], dmsg->len);
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else
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return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1],
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dmsg->buf[0], dmsg->len - 1);
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}
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static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr,
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uint chip_flags)
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{
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struct intel_i2c *i2c = dev_get_priv(bus);
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u8 buf[4];
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return smbus_block_read(i2c->base, chip_addr, buf, 0, 1);
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}
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static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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return 0;
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}
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static int intel_i2c_probe(struct udevice *dev)
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{
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struct intel_i2c *priv = dev_get_priv(dev);
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ulong base;
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/* Save base address from PCI BAR */
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priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, 0, 0, PCI_REGION_TYPE,
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PCI_REGION_IO);
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base = priv->base;
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/* Set SMBus enable. */
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dm_pci_write_config8(dev, HOSTC, HST_EN);
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/* Disable interrupts */
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outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL);
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/* Set 32-byte data buffer mode */
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outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL);
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return 0;
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}
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static int intel_i2c_bind(struct udevice *dev)
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{
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char name[20];
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/* Create a unique device name for PCI type devices */
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if (device_is_on_pci_bus(dev)) {
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sprintf(name, "intel_i2c#%u", dev_seq(dev));
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device_set_name(dev, name);
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}
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return 0;
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}
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static const struct dm_i2c_ops intel_i2c_ops = {
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.xfer = intel_i2c_xfer,
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.probe_chip = intel_i2c_probe_chip,
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.set_bus_speed = intel_i2c_set_bus_speed,
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};
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static const struct udevice_id intel_i2c_ids[] = {
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{ .compatible = "intel,ich-i2c" },
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{ }
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};
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U_BOOT_DRIVER(intel_i2c) = {
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.name = "i2c_intel",
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.id = UCLASS_I2C,
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.of_match = intel_i2c_ids,
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.ops = &intel_i2c_ops,
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.priv_auto = sizeof(struct intel_i2c),
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.bind = intel_i2c_bind,
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.probe = intel_i2c_probe,
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};
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static struct pci_device_id intel_smbus_pci_supported[] = {
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/* Intel BayTrail SMBus on the PCI bus */
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{ PCI_VDEVICE(INTEL, 0x0f12) },
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/* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */
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{ PCI_VDEVICE(INTEL, 0x1e22) },
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{},
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};
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U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported);
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