mirror of
https://github.com/AsahiLinux/u-boot
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6d133b3158
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.
Reported-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Fixes: 0dc0d1e094
("i2c: Add Microchip PolarFire SoC I2C driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Removed Tag by hs: Fixes: 0190d48488 ("i2c: microchip: fix ack sending logic")
493 lines
11 KiB
C
493 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Microchip I2C controller driver
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*
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* Copyright (C) 2021-2022 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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* Conor Dooley <conor.dooley@microchip.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#define MICROCHIP_I2C_TIMEOUT (1000 * 60)
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#define MPFS_I2C_CTRL (0x00)
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#define CTRL_CR0 (0x00)
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#define CTRL_CR1 (0x01)
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#define CTRL_AA BIT(2)
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#define CTRL_SI BIT(3)
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#define CTRL_STO BIT(4)
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#define CTRL_STA BIT(5)
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#define CTRL_ENS1 BIT(6)
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#define CTRL_CR2 (0x07)
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#define MPFS_I2C_STATUS (0x04)
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#define STATUS_BUS_ERROR (0x00)
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#define STATUS_M_START_SENT (0x08)
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#define STATUS_M_REPEATED_START_SENT (0x10)
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#define STATUS_M_SLAW_ACK (0x18)
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#define STATUS_M_SLAW_NACK (0x20)
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#define STATUS_M_TX_DATA_ACK (0x28)
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#define STATUS_M_TX_DATA_NACK (0x30)
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#define STATUS_M_ARB_LOST (0x38)
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#define STATUS_M_SLAR_ACK (0x40)
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#define STATUS_M_SLAR_NACK (0x48)
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#define STATUS_M_RX_DATA_ACKED (0x50)
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#define STATUS_M_RX_DATA_NACKED (0x58)
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#define STATUS_S_SLAW_ACKED (0x60)
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#define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
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#define STATUS_S_GENERAL_CALL_ACKED (0x70)
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#define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
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#define STATUS_S_RX_DATA_ACKED (0x80)
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#define STATUS_S_RX_DATA_NACKED (0x88)
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#define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
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#define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
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#define STATUS_S_RX_STOP (0xA0)
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#define STATUS_S_SLAR_ACKED (0xA8)
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#define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
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#define STATUS_S_TX_DATA_ACK (0xb8)
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#define STATUS_S_TX_DATA_NACK (0xC0)
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#define STATUS_LAST_DATA_ACK (0xC8)
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#define STATUS_M_SMB_MASTER_RESET (0xD0)
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#define STATUS_S_SCL_LOW_TIMEOUT (0xD8)
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#define STATUS_NO_STATE_INFO (0xF8)
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#define MPFS_I2C_DATA (0x08)
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#define MPFS_I2C_SLAVE0_ADDR (0x0c)
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#define MPFS_I2C_SMBUS (0x10)
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#define MPFS_I2C_FREQ (0x14)
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#define MPFS_I2C_GLITCHREG (0x18)
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#define MPFS_I2C_SLAVE1_ADDR (0x1c)
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#define PCLK_DIV_256 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
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#define PCLK_DIV_224 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
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#define PCLK_DIV_192 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
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#define PCLK_DIV_160 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
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#define PCLK_DIV_960 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
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#define PCLK_DIV_120 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
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#define PCLK_DIV_60 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
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#define BCLK_DIV_8 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
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#define CLK_MASK ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
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/*
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* mpfs_i2c_bus - I2C bus context
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* @base: pointer to register struct
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* @msg_len: number of bytes transferred in msg
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* @msg_err: error code for completed message
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* @i2c_clk: clock reference for i2c input clock
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* @clk_rate: current i2c bus clock rate
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* @buf: ptr to msg buffer for easier use.
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* @addr: i2c address.
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* @isr_status: cached copy of local ISR status.
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*/
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struct mpfs_i2c_bus {
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void __iomem *base;
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size_t msg_len;
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int msg_err;
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struct clk i2c_clk;
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u32 clk_rate;
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u8 *buf;
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u8 addr;
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u32 isr_status;
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};
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static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
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{
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return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
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}
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static void mpfs_i2c_int_clear(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_SI;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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}
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static void mpfs_i2c_core_disable(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_ENS1;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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}
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static void mpfs_i2c_core_enable(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_ENS1;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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}
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static void mpfs_i2c_reset(struct mpfs_i2c_bus *bus)
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{
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mpfs_i2c_core_disable(bus);
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mpfs_i2c_core_enable(bus);
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}
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static inline void mpfs_i2c_stop(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_STO;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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}
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static inline int mpfs_generate_divisor(u32 rate, u8 *code)
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{
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int ret = 0;
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if (rate >= 960)
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*code = PCLK_DIV_960;
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else if (rate >= 256)
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*code = PCLK_DIV_256;
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else if (rate >= 224)
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*code = PCLK_DIV_224;
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else if (rate >= 192)
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*code = PCLK_DIV_192;
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else if (rate >= 160)
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*code = PCLK_DIV_160;
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else if (rate >= 120)
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*code = PCLK_DIV_120;
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else if (rate >= 60)
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*code = PCLK_DIV_60;
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else if (rate >= 8)
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*code = BCLK_DIV_8;
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else
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ret = -EINVAL;
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return ret;
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}
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static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev)
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{
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u32 clk_rate, divisor;
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u8 clkval, ctrl;
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int ret;
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ret = clk_get_by_index(dev, 0, &bus->i2c_clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&bus->i2c_clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&bus->i2c_clk);
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if (!clk_rate)
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return -EINVAL;
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clk_free(&bus->i2c_clk);
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divisor = clk_rate / bus->clk_rate;
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CLK_MASK;
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ret = mpfs_generate_divisor(divisor, &clkval);
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if (ret)
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return -EINVAL;
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ctrl |= clkval;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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/* Reset I2C core */
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mpfs_i2c_reset(bus);
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return 0;
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}
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static void mpfs_i2c_transfer(struct mpfs_i2c_bus *bus, u32 data)
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{
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if (bus->msg_len > 0)
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writel(data, bus->base + MPFS_I2C_DATA);
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}
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static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl;
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u8 data_read;
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if (bus->msg_len > 0) {
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data_read = readl(bus->base + MPFS_I2C_DATA);
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*bus->buf++ = data_read;
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bus->msg_len--;
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}
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if (bus->msg_len <= 1) {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_AA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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}
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}
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static int mpfs_i2c_fill_tx(struct mpfs_i2c_bus *bus)
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{
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mpfs_i2c_transfer(bus, *bus->buf++);
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bus->msg_len--;
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return 0;
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}
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static int mpfs_i2c_service_handler(struct mpfs_i2c_bus *bus)
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{
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bool finish = false;
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u32 status;
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u8 ctrl;
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status = bus->isr_status;
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switch (status) {
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case STATUS_M_START_SENT:
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case STATUS_M_REPEATED_START_SENT:
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_STA;
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writel(bus->addr, bus->base + MPFS_I2C_DATA);
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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break;
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case STATUS_M_SLAW_ACK:
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case STATUS_M_TX_DATA_ACK:
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if (bus->msg_len > 0) {
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mpfs_i2c_fill_tx(bus);
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} else {
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/* On the last byte to be transmitted, send STOP */
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mpfs_i2c_stop(bus);
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finish = true;
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}
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break;
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case STATUS_M_SLAR_ACK:
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if (bus->msg_len > 1u) {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_AA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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} else if (bus->msg_len == 1u) {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_AA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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} else {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_AA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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/* On the last byte to be transmitted, send STOP */
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mpfs_i2c_stop(bus);
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finish = true;
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}
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break;
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case STATUS_M_RX_DATA_ACKED:
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mpfs_i2c_empty_rx(bus);
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break;
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case STATUS_M_RX_DATA_NACKED:
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mpfs_i2c_empty_rx(bus);
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if (bus->msg_len == 0) {
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/* On the last byte to be transmitted, send STOP */
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mpfs_i2c_stop(bus);
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finish = true;
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}
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break;
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case STATUS_M_TX_DATA_NACK:
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case STATUS_M_SLAR_NACK:
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case STATUS_M_SLAW_NACK:
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bus->msg_err = -ENXIO;
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mpfs_i2c_stop(bus);
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finish = true;
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break;
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case STATUS_M_ARB_LOST:
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/* Handle Lost Arbitration */
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bus->msg_err = -EAGAIN;
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finish = true;
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break;
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default:
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break;
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}
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if (finish) {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl &= ~CTRL_AA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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return 0;
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}
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return 1;
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}
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static int mpfs_i2c_service(struct mpfs_i2c_bus *bus)
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{
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int ret = 0;
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int si_bit;
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si_bit = readl(bus->base + MPFS_I2C_CTRL);
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if (si_bit & CTRL_SI) {
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bus->isr_status = readl(bus->base + MPFS_I2C_STATUS);
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ret = mpfs_i2c_service_handler(bus);
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}
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/* Clear the si flag */
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mpfs_i2c_int_clear(bus);
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si_bit = readl(bus->base + MPFS_I2C_CTRL);
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return ret;
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}
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static int mpfs_i2c_check_service_change(struct mpfs_i2c_bus *bus)
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{
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u8 ctrl;
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u32 count = 0;
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while (1) {
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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if (ctrl & CTRL_SI)
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break;
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udelay(1);
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count += 1;
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if (count == MICROCHIP_I2C_TIMEOUT)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int mpfs_i2c_poll_device(struct mpfs_i2c_bus *bus)
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{
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int ret;
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while (1) {
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ret = mpfs_i2c_check_service_change(bus);
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if (ret)
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return ret;
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ret = mpfs_i2c_service(bus);
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if (!ret)
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/* all messages have been transferred */
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return ret;
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}
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}
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static int mpfs_i2c_xfer_msg(struct mpfs_i2c_bus *bus, struct i2c_msg *msg)
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{
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u8 ctrl;
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int ret;
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if (!msg->len || !msg->buf)
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return -EINVAL;
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bus->addr = i2c_8bit_addr_from_msg(msg);
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bus->msg_len = msg->len;
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bus->buf = msg->buf;
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bus->msg_err = 0;
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mpfs_i2c_core_enable(bus);
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_STA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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ret = mpfs_i2c_poll_device(bus);
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if (ret)
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return ret;
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return bus->msg_err;
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}
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static int mpfs_i2c_xfer(struct udevice *dev, struct i2c_msg *msgs, int num_msgs)
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{
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struct mpfs_i2c_bus *bus = dev_get_priv(dev);
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int idx, ret;
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if (!msgs || !num_msgs)
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return -EINVAL;
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for (idx = 0; idx < num_msgs; idx++) {
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ret = mpfs_i2c_xfer_msg(bus, msgs++);
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if (ret)
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return ret;
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}
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return ret;
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}
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static int mpfs_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
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{
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struct mpfs_i2c_bus *bus = dev_get_priv(dev);
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int ret;
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u8 ctrl, reg = 0;
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/*
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* Send the chip address and verify that the
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* address was <ACK>ed.
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*/
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bus->addr = addr << 1 | I2C_M_RD;
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bus->buf = ®
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bus->msg_len = 0;
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bus->msg_err = 0;
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mpfs_i2c_core_enable(bus);
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ctrl = readl(bus->base + MPFS_I2C_CTRL);
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ctrl |= CTRL_STA;
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writel(ctrl, bus->base + MPFS_I2C_CTRL);
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ret = mpfs_i2c_poll_device(bus);
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if (ret)
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return ret;
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return bus->msg_err;
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}
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static int mpfs_i2c_probe(struct udevice *dev)
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{
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int ret;
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u32 val;
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struct mpfs_i2c_bus *bus = dev_get_priv(dev);
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bus->base = dev_read_addr_ptr(dev);
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if (!bus->base)
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return -EINVAL;
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val = dev_read_u32(dev, "clock-frequency", &bus->clk_rate);
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if (val) {
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printf("Default to 100kHz\n");
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/* default clock rate */
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bus->clk_rate = 100000;
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}
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if (bus->clk_rate > 400000 || bus->clk_rate <= 0) {
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printf("Invalid clock-frequency %d\n", bus->clk_rate);
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return -EINVAL;
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}
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ret = mpfs_i2c_init(bus, dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dm_i2c_ops mpfs_i2c_ops = {
|
|
.xfer = mpfs_i2c_xfer,
|
|
.probe_chip = mpfs_i2c_probe_chip,
|
|
};
|
|
|
|
static const struct udevice_id mpfs_i2c_ids[] = {
|
|
{.compatible = "microchip,mpfs-i2c"},
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(mpfs_i2c) = {
|
|
.name = "mpfs_i2c",
|
|
.id = UCLASS_I2C,
|
|
.of_match = mpfs_i2c_ids,
|
|
.ops = &mpfs_i2c_ops,
|
|
.probe = mpfs_i2c_probe,
|
|
.priv_auto = sizeof(struct mpfs_i2c_bus),
|
|
};
|