mirror of
https://github.com/AsahiLinux/u-boot
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f76f86029d
During sequential loading of data, hold the bus to prevent controller from sending stop signal in case no data is available in fifo. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/2407b39d305999cb42438c5423aebc3b514acabb.1646122610.git.michal.simek@xilinx.com
524 lines
14 KiB
C
524 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
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* IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
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*
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* This file is based on: drivers/i2c/zynq_i2c.c,
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* with added driver-model support and code cleanup.
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <dm/device_compat.h>
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#include <dm/root.h>
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#include <i2c.h>
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#include <fdtdec.h>
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#include <mapmem.h>
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#include <wait_bit.h>
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#include <clk.h>
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/* i2c register set */
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struct cdns_i2c_regs {
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u32 control;
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u32 status;
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u32 address;
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u32 data;
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u32 interrupt_status;
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u32 transfer_size;
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u32 slave_mon_pause;
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u32 time_out;
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u32 interrupt_mask;
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u32 interrupt_enable;
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u32 interrupt_disable;
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};
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/* Control register fields */
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#define CDNS_I2C_CONTROL_RW 0x00000001
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#define CDNS_I2C_CONTROL_MS 0x00000002
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#define CDNS_I2C_CONTROL_NEA 0x00000004
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#define CDNS_I2C_CONTROL_ACKEN 0x00000008
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#define CDNS_I2C_CONTROL_HOLD 0x00000010
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#define CDNS_I2C_CONTROL_SLVMON 0x00000020
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#define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
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#define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
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#define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
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#define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
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#define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
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/* Status register values */
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#define CDNS_I2C_STATUS_RXDV 0x00000020
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#define CDNS_I2C_STATUS_TXDV 0x00000040
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#define CDNS_I2C_STATUS_RXOVF 0x00000080
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#define CDNS_I2C_STATUS_BA 0x00000100
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/* Interrupt register fields */
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#define CDNS_I2C_INTERRUPT_COMP 0x00000001
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#define CDNS_I2C_INTERRUPT_DATA 0x00000002
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#define CDNS_I2C_INTERRUPT_NACK 0x00000004
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#define CDNS_I2C_INTERRUPT_TO 0x00000008
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#define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
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#define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
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#define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
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#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
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#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
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#define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
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CDNS_I2C_INTERRUPT_DATA | \
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CDNS_I2C_INTERRUPT_NACK | \
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CDNS_I2C_INTERRUPT_TO | \
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CDNS_I2C_INTERRUPT_SLVRDY | \
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CDNS_I2C_INTERRUPT_RXOVF | \
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CDNS_I2C_INTERRUPT_TXOVF | \
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CDNS_I2C_INTERRUPT_RXUNF | \
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CDNS_I2C_INTERRUPT_ARBLOST)
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#define CDNS_I2C_FIFO_DEPTH 16
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#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
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#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
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#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
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#define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
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#ifdef DEBUG
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static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
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{
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int int_status;
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int status;
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int_status = readl(&cdns_i2c->interrupt_status);
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status = readl(&cdns_i2c->status);
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if (int_status || status) {
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debug("Status: ");
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if (int_status & CDNS_I2C_INTERRUPT_COMP)
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debug("COMP ");
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if (int_status & CDNS_I2C_INTERRUPT_DATA)
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debug("DATA ");
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if (int_status & CDNS_I2C_INTERRUPT_NACK)
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debug("NACK ");
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if (int_status & CDNS_I2C_INTERRUPT_TO)
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debug("TO ");
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if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
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debug("SLVRDY ");
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if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
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debug("RXOVF ");
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if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
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debug("TXOVF ");
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if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
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debug("RXUNF ");
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if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
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debug("ARBLOST ");
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if (status & CDNS_I2C_STATUS_RXDV)
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debug("RXDV ");
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if (status & CDNS_I2C_STATUS_TXDV)
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debug("TXDV ");
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if (status & CDNS_I2C_STATUS_RXOVF)
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debug("RXOVF ");
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if (status & CDNS_I2C_STATUS_BA)
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debug("BA ");
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debug("TS%d ", readl(&cdns_i2c->transfer_size));
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debug("\n");
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}
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}
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#endif
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struct i2c_cdns_bus {
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int id;
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unsigned int input_freq;
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struct cdns_i2c_regs __iomem *regs; /* register base */
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int hold_flag;
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u32 quirks;
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};
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struct cdns_i2c_platform_data {
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u32 quirks;
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};
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/* Wait for an interrupt */
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static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
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{
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int timeout, int_status;
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for (timeout = 0; timeout < 100; timeout++) {
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int_status = readl(&cdns_i2c->interrupt_status);
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if (int_status & mask)
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break;
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udelay(100);
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}
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/* Clear interrupt status flags */
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writel(int_status & mask, &cdns_i2c->interrupt_status);
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return int_status & mask;
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}
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#define CDNS_I2C_DIVA_MAX 4
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#define CDNS_I2C_DIVB_MAX 64
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static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
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unsigned int *a, unsigned int *b)
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{
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unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
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unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
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unsigned int last_error, current_error;
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/* calculate (divisor_a+1) x (divisor_b+1) */
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temp = input_clk / (22 * fscl);
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/*
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* If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
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* the fscl input is out of range. Return error.
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*/
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if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
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return -EINVAL;
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last_error = -1;
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for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
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div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
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if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
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continue;
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div_b--;
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actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
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if (actual_fscl > fscl)
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continue;
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current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
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(fscl - actual_fscl));
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if (last_error > current_error) {
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calc_div_a = div_a;
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calc_div_b = div_b;
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best_fscl = actual_fscl;
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last_error = current_error;
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}
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}
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*a = calc_div_a;
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*b = calc_div_b;
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*f = best_fscl;
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return 0;
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}
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static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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struct i2c_cdns_bus *bus = dev_get_priv(dev);
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u32 div_a = 0, div_b = 0;
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unsigned long speed_p = speed;
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int ret = 0;
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if (speed > I2C_SPEED_FAST_RATE) {
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debug("%s, failed to set clock speed to %u\n", __func__,
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speed);
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return -EINVAL;
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}
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ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
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if (ret)
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return ret;
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debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
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__func__, div_a, div_b, bus->input_freq, speed, speed_p);
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writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
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(div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
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/* Enable master mode, ack, and 7-bit addressing */
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setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
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CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
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return 0;
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}
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static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
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{
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return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
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}
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static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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u32 ret;
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bool start = 1;
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/* Set the controller in Master transmit mode and clear FIFO */
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
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/*
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* For sequential data load hold the bus.
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*/
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if (len > 1)
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setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Clear the interrupts in status register */
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writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
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/* In case of Probe (i.e no data), start the transfer */
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if (!len)
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writel(addr, ®s->address);
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while (len-- && !is_arbitration_lost(regs)) {
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writel(*(cur_data++), ®s->data);
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/* Trigger write only after loading data */
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if (start) {
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writel(addr, ®s->address);
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start = 0;
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}
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if (len && readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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if (ret & CDNS_I2C_INTERRUPT_COMP)
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continue;
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/* Release the bus */
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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}
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if (len && is_arbitration_lost(regs))
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return -EAGAIN;
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/* All done... release the bus */
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if (!i2c_bus->hold_flag)
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Wait for the address and data to be sent */
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
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CDNS_I2C_INTERRUPT_COMP)))
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return -ETIMEDOUT;
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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return 0;
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}
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static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
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{
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return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
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}
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static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 recv_count)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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u32 curr_recv_count;
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int updatetx, hold_quirk;
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u32 ret;
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curr_recv_count = recv_count;
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/* Check for the message size against the FIFO depth */
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if (recv_count > CDNS_I2C_FIFO_DEPTH)
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setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
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CDNS_I2C_CONTROL_RW);
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if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
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writel(curr_recv_count, ®s->transfer_size);
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} else {
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writel(recv_count, ®s->transfer_size);
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}
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/* Start reading data */
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writel(addr, ®s->address);
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updatetx = recv_count > curr_recv_count;
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hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
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while (recv_count && !is_arbitration_lost(regs)) {
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while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
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if (recv_count < CDNS_I2C_FIFO_DEPTH &&
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!i2c_bus->hold_flag) {
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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}
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*(cur_data)++ = readl(®s->data);
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recv_count--;
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curr_recv_count--;
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if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
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break;
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}
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if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
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/* wait while fifo is full */
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while (readl(®s->transfer_size) !=
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(curr_recv_count - CDNS_I2C_FIFO_DEPTH))
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;
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/*
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* Check number of bytes to be received against maximum
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* transfer size and update register accordingly.
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*/
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if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
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CDNS_I2C_TRANSFER_SIZE) {
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writel(CDNS_I2C_TRANSFER_SIZE,
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®s->transfer_size);
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
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CDNS_I2C_FIFO_DEPTH;
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} else {
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writel(recv_count - CDNS_I2C_FIFO_DEPTH,
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®s->transfer_size);
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curr_recv_count = recv_count;
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}
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} else if (recv_count && !hold_quirk && !curr_recv_count) {
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if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
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writel(CDNS_I2C_TRANSFER_SIZE,
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®s->transfer_size);
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curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
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} else {
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writel(recv_count, ®s->transfer_size);
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curr_recv_count = recv_count;
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}
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writel(addr, ®s->address);
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}
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}
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/* Wait for the address and data to be sent */
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
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CDNS_I2C_INTERRUPT_COMP)))
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return -ETIMEDOUT;
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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return 0;
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}
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static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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int ret = 0;
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int count;
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bool hold_quirk;
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struct i2c_msg *message = msg;
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int num_msgs = nmsgs;
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hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
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if (nmsgs > 1) {
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/*
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* This controller does not give completion interrupt after a
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* master receive message if HOLD bit is set (repeated start),
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* resulting in SW timeout. Hence, if a receive message is
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* followed by any other message, an error is returned
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* indicating that this sequence is not supported.
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*/
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for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
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if (msg[count].flags & I2C_M_RD) {
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printf("Can't do repeated start after a receive message\n");
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return -EOPNOTSUPP;
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}
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}
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i2c_bus->hold_flag = 1;
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setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
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} else {
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i2c_bus->hold_flag = 0;
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}
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
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nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
|
|
msg->len);
|
|
} else {
|
|
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
|
|
msg->len);
|
|
}
|
|
if (ret == -EAGAIN) {
|
|
msg = message;
|
|
nmsgs = num_msgs;
|
|
retry++;
|
|
printf("%s,arbitration lost, retrying:%d\n", __func__,
|
|
retry);
|
|
continue;
|
|
}
|
|
|
|
if (ret) {
|
|
debug("i2c_write: error sending\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cdns_i2c_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
|
|
struct cdns_i2c_platform_data *pdata =
|
|
(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
|
|
struct clk clk;
|
|
int ret;
|
|
|
|
i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev);
|
|
if (!i2c_bus->regs)
|
|
return -ENOMEM;
|
|
|
|
if (pdata)
|
|
i2c_bus->quirks = pdata->quirks;
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i2c_bus->input_freq = clk_get_rate(&clk);
|
|
|
|
ret = clk_enable(&clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_i2c_ops cdns_i2c_ops = {
|
|
.xfer = cdns_i2c_xfer,
|
|
.set_bus_speed = cdns_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct cdns_i2c_platform_data r1p10_i2c_def = {
|
|
.quirks = CDNS_I2C_BROKEN_HOLD_BIT,
|
|
};
|
|
|
|
static const struct udevice_id cdns_i2c_of_match[] = {
|
|
{ .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
|
|
{ .compatible = "cdns,i2c-r1p14" },
|
|
{ /* end of table */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(cdns_i2c) = {
|
|
.name = "i2c_cdns",
|
|
.id = UCLASS_I2C,
|
|
.of_match = cdns_i2c_of_match,
|
|
.of_to_plat = cdns_i2c_of_to_plat,
|
|
.priv_auto = sizeof(struct i2c_cdns_bus),
|
|
.ops = &cdns_i2c_ops,
|
|
};
|