mirror of
https://github.com/AsahiLinux/u-boot
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599474120a
The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
279 lines
6.7 KiB
C
279 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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*
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* Peng Fan <peng.fan at nxp.com>
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*/
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#include <linux/bitops.h>
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#ifdef CONFIG_IMX8MQ
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#include <asm/arch/clock_imx8mq.h>
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#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \
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defined(CONFIG_IMX8MP)
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#include <asm/arch/clock_imx8mm.h>
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#else
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#error "Error no clock.h"
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#endif
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#define MHZ(X) ((X) * 1000000UL)
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/* Mainly for compatible to imx common code. */
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_IPG_CLK,
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MXC_CSPI_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_I2C_CLK,
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MXC_UART_CLK,
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MXC_QSPI_CLK,
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};
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enum clk_slice_type {
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CORE_CLOCK_SLICE,
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BUS_CLOCK_SLICE,
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IP_CLOCK_SLICE,
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AHB_CLOCK_SLICE,
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IPG_CLOCK_SLICE,
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CORE_SEL_CLOCK_SLICE,
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DRAM_SEL_CLOCK_SLICE,
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};
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enum root_pre_div {
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CLK_ROOT_PRE_DIV1 = 0,
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CLK_ROOT_PRE_DIV2,
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CLK_ROOT_PRE_DIV3,
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CLK_ROOT_PRE_DIV4,
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CLK_ROOT_PRE_DIV5,
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CLK_ROOT_PRE_DIV6,
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CLK_ROOT_PRE_DIV7,
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CLK_ROOT_PRE_DIV8,
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};
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enum root_post_div {
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CLK_ROOT_POST_DIV1 = 0,
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CLK_ROOT_POST_DIV2,
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CLK_ROOT_POST_DIV3,
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CLK_ROOT_POST_DIV4,
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CLK_ROOT_POST_DIV5,
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CLK_ROOT_POST_DIV6,
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CLK_ROOT_POST_DIV7,
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CLK_ROOT_POST_DIV8,
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CLK_ROOT_POST_DIV9,
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CLK_ROOT_POST_DIV10,
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CLK_ROOT_POST_DIV11,
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CLK_ROOT_POST_DIV12,
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CLK_ROOT_POST_DIV13,
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CLK_ROOT_POST_DIV14,
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CLK_ROOT_POST_DIV15,
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CLK_ROOT_POST_DIV16,
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CLK_ROOT_POST_DIV17,
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CLK_ROOT_POST_DIV18,
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CLK_ROOT_POST_DIV19,
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CLK_ROOT_POST_DIV20,
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CLK_ROOT_POST_DIV21,
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CLK_ROOT_POST_DIV22,
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CLK_ROOT_POST_DIV23,
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CLK_ROOT_POST_DIV24,
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CLK_ROOT_POST_DIV25,
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CLK_ROOT_POST_DIV26,
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CLK_ROOT_POST_DIV27,
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CLK_ROOT_POST_DIV28,
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CLK_ROOT_POST_DIV29,
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CLK_ROOT_POST_DIV30,
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CLK_ROOT_POST_DIV31,
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CLK_ROOT_POST_DIV32,
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CLK_ROOT_POST_DIV33,
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CLK_ROOT_POST_DIV34,
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CLK_ROOT_POST_DIV35,
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CLK_ROOT_POST_DIV36,
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CLK_ROOT_POST_DIV37,
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CLK_ROOT_POST_DIV38,
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CLK_ROOT_POST_DIV39,
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CLK_ROOT_POST_DIV40,
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CLK_ROOT_POST_DIV41,
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CLK_ROOT_POST_DIV42,
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CLK_ROOT_POST_DIV43,
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CLK_ROOT_POST_DIV44,
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CLK_ROOT_POST_DIV45,
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CLK_ROOT_POST_DIV46,
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CLK_ROOT_POST_DIV47,
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CLK_ROOT_POST_DIV48,
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CLK_ROOT_POST_DIV49,
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CLK_ROOT_POST_DIV50,
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CLK_ROOT_POST_DIV51,
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CLK_ROOT_POST_DIV52,
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CLK_ROOT_POST_DIV53,
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CLK_ROOT_POST_DIV54,
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CLK_ROOT_POST_DIV55,
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CLK_ROOT_POST_DIV56,
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CLK_ROOT_POST_DIV57,
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CLK_ROOT_POST_DIV58,
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CLK_ROOT_POST_DIV59,
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CLK_ROOT_POST_DIV60,
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CLK_ROOT_POST_DIV61,
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CLK_ROOT_POST_DIV62,
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CLK_ROOT_POST_DIV63,
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CLK_ROOT_POST_DIV64,
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};
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struct clk_root_map {
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enum clk_root_index entry;
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enum clk_slice_type slice_type;
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u32 slice_index;
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u8 src_mux[8];
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};
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struct ccm_ccgr {
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u32 ccgr;
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u32 ccgr_set;
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u32 ccgr_clr;
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u32 ccgr_tog;
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};
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struct ccm_root {
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u32 target_root;
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u32 target_root_set;
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u32 target_root_clr;
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u32 target_root_tog;
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u32 misc;
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u32 misc_set;
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u32 misc_clr;
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u32 misc_tog;
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u32 nm_post;
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u32 nm_post_root_set;
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u32 nm_post_root_clr;
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u32 nm_post_root_tog;
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u32 nm_pre;
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u32 nm_pre_root_set;
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u32 nm_pre_root_clr;
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u32 nm_pre_root_tog;
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u32 db_post;
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u32 db_post_root_set;
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u32 db_post_root_clr;
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u32 db_post_root_tog;
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u32 db_pre;
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u32 db_pre_root_set;
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u32 db_pre_root_clr;
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u32 db_pre_root_tog;
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u32 reserved[4];
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u32 access_ctrl;
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u32 access_ctrl_root_set;
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u32 access_ctrl_root_clr;
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u32 access_ctrl_root_tog;
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};
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struct ccm_reg {
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u32 reserved_0[4096];
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struct ccm_ccgr ccgr_array[192];
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u32 reserved_1[3328];
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struct ccm_root core_root[5];
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u32 reserved_2[352];
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struct ccm_root bus_root[12];
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u32 reserved_3[128];
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struct ccm_root ahb_ipg_root[4];
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u32 reserved_4[384];
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struct ccm_root dram_sel;
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struct ccm_root core_sel;
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u32 reserved_5[448];
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struct ccm_root ip_root[78];
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};
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enum enet_freq {
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ENET_25MHZ = 0,
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ENET_50MHZ,
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ENET_125MHZ,
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};
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#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
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{ \
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.clk = (_rate), \
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.alt_root_sel = (_m), \
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.alt_pre_div = (_p), \
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.apb_root_sel = (_s), \
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.apb_pre_div = (_k), \
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}
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struct dram_bypass_clk_setting {
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ulong clk;
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int alt_root_sel;
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enum root_pre_div alt_pre_div;
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int apb_root_sel;
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enum root_pre_div apb_pre_div;
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};
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#define CCGR_CLK_ON_MASK 0x03
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#define CLK_SRC_ON_MASK 0x03
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#define CLK_ROOT_ON BIT(28)
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#define CLK_ROOT_OFF (0 << 28)
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#define CLK_ROOT_ENABLE_MASK BIT(28)
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#define CLK_ROOT_ENABLE_SHIFT 28
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#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
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/* For SEL, only use 1 bit */
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#define CLK_ROOT_SRC_MUX_MASK 0x07000000
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#define CLK_ROOT_SRC_MUX_SHIFT 24
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#define CLK_ROOT_SRC_0 0x00000000
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#define CLK_ROOT_SRC_1 0x01000000
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#define CLK_ROOT_SRC_2 0x02000000
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#define CLK_ROOT_SRC_3 0x03000000
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#define CLK_ROOT_SRC_4 0x04000000
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#define CLK_ROOT_SRC_5 0x05000000
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#define CLK_ROOT_SRC_6 0x06000000
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#define CLK_ROOT_SRC_7 0x07000000
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#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
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#define CLK_ROOT_PRE_DIV_SHIFT 16
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#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
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#define CLK_ROOT_AUDO_SLOW_EN 0x1000
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#define CLK_ROOT_AUDO_DIV_MASK 0x700
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#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
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#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
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/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
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#define CLK_ROOT_POST_DIV_MASK 0x3f
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#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
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#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
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#define CLK_ROOT_POST_DIV_SHIFT 0
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#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
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#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
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#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
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#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
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#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
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#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
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#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
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#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
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void dram_pll_init(ulong pll_val);
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void dram_enable_bypass(ulong clk_val);
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void dram_disable_bypass(void);
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u32 imx_get_fecclk(void);
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u32 imx_get_uartclk(void);
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int clock_init(void);
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void init_clk_usdhc(u32 index);
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void init_nand_clk(void);
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void init_uart_clk(u32 index);
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void init_usb_clk(void);
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void init_wdog_clk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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int clock_enable(enum clk_ccgr_index index, bool enable);
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int clock_root_enabled(enum clk_root_index clock_id);
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int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
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enum root_post_div post_div, enum clk_root_src clock_src);
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int clock_set_target_val(enum clk_root_index clock_id, u32 val);
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int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
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int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
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int clock_get_postdiv(enum clk_root_index clock_id,
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enum root_post_div *post_div);
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int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
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void mxs_set_lcdclk(u32 base_addr, u32 freq);
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int set_clk_qspi(void);
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void enable_ocotp_clk(unsigned char enable);
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int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
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int set_clk_enet(enum enet_freq type);
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void hab_caam_clock_enable(unsigned char enable);
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