u-boot/board/synopsys
Eugeniy Paltsev 4e782b5940 ARC: HSDK: Fixup DW SDIO CIU frequency to 50000000Hz
DW SDIO controller has external CIU clock divider controlled via
register in the SDIO IP. Due to its unexpected default value
(we expected it to divide by 1 but in reality it divides by 8)
SDIO IP uses wrong CIU clock (it should be 100000000Hz but actual
is 12500000Hz) and works unstable (see STAR 9001204800).

So increase SDIO CIU frequency from actual 12500000Hz to 50000000Hz
by switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11 11:36:22 +03:00
..
axs10x axs103: Support slave core kick-start on axs103 v1.1 firmware 2017-03-31 22:09:36 +03:00
hsdk ARC: HSDK: Fixup DW SDIO CIU frequency to 50000000Hz 2017-12-11 11:36:22 +03:00
Kconfig arc: Rename ARCangel4 board to nSIM 2016-08-05 12:50:25 +03:00
MAINTAINERS arc: Rename ARCangel4 board to nSIM 2016-08-05 12:50:25 +03:00