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552e7c57d0
Add support for Cortina CS4223 10G PHY
- As per the CS4223 specs, an EEPROM module is
connected to the PHY. At startup the PHY reads
the firmware line and tries to load the firmware
into the internal memory.
- This driver reads the EEPROM status
and checks if firmware has been loaded
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
78 lines
2.8 KiB
C
78 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Cortina PHY drivers
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#ifndef _CORTINA_H_
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#define _CORTINA_H_
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#define VILLA_GLOBAL_CHIP_ID_LSB 0x000
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#define VILLA_GLOBAL_CHIP_ID_MSB 0x001
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#define VILLA_GLOBAL_BIST_CONTROL 0x002
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#define VILLA_GLOBAL_BIST_STATUS 0x003
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#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007
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#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008
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#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A
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#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B
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#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E
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#define VILLA_MSEQ_OPTIONS 0x1D0
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#define VILLA_MSEQ_PC 0x1D3
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#define VILLA_MSEQ_BANKSELECT 0x1DF
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#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB
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#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E
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#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403
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#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404
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#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405
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#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369
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#define VILLA_MSEQ_ENABLE_MSB 0x194
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#define VILLA_MSEQ_SPARE21_LSB 0x226
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#define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0
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#define VILLA_MSEQ_SPARE12_MSB 0x215
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#define VILLA_MSEQ_SPARE2_LSB 0x200
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#define VILLA_MSEQ_SPARE7_LSB 0x20A
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#define VILLA_MSEQ_SPARE9_LSB 0x20E
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#define VILLA_MSEQ_SPARE3_LSB 0x202
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#define VILLA_MSEQ_SPARE3_MSB 0x203
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#define VILLA_MSEQ_SPARE8_LSB 0x20C
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#define VILLA_MSEQ_SPARE8_MSB 0x20D
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#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2
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#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4
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#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6
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#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8
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#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA
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#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC
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#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0
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#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE
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#define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2
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#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2
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#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360
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#define VILLA_MSEQ_POWER_DOWN_LSB 0x198
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#define VILLA_MSEQ_POWER_DOWN_MSB 0x199
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#define VILLA_MSEQ_CAL_RX_SLICER 0x1B8
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#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365
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#define VILLA_MSEQ_COEF_INIT_SEL 0x1AE
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#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A
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#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195
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#define VILLA_MSEQ_SPARE25_LSB 0x22E
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#define VILLA_MSEQ_SPARE23_LSB 0x22A
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#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA
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#define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030
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#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812
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#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813
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#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427
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#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428
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/* Cortina CS4223 */
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#define CS4223_EEPROM_STATUS 0x5001
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#define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1
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#define mseq_edc_bist_done (0x1<<0)
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#define mseq_edc_bist_fail (0x1<<8)
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struct cortina_reg_config {
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unsigned short reg_addr;
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unsigned short reg_value;
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};
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#endif
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