mirror of
https://github.com/AsahiLinux/u-boot
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4f51064533
Add support for Rockchip rk3588 variant of pinctrl. The driver is adapted from the Linux driver. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> [eugen.hristev@collabora.com: port to latest U-boot, bring more changes from Linux use translated pull values table] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
353 lines
11 KiB
C
353 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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#include <dt-bindings/pinctrl/rockchip.h>
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static int rk3588_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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struct regmap *regmap;
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int iomux_num = (pin / 8);
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int reg, ret, mask;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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regmap = priv->regmap_base;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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if (bank->bank_num == 0) {
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if (pin >= RK_PB4 && pin <= RK_PD7) {
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if (mux < 8) {
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reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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} else {
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u32 reg0 = 0;
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reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
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data = (mask << (bit + 16));
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data |= 8 << bit;
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ret = regmap_write(regmap, reg0, data);
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reg0 = reg + 0x8000; /* BUS_IOC_BASE */
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data = (mask << (bit + 16));
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data |= mux << bit;
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regmap = priv->regmap_base;
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regmap_write(regmap, reg0, data);
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}
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} else {
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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}
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return ret;
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} else if (bank->bank_num > 0) {
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reg += 0x8000; /* BUS_IOC_BASE */
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}
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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return regmap_write(regmap, reg, data);
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}
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#define RK3588_PMU1_IOC_REG (0x0000)
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#define RK3588_PMU2_IOC_REG (0x4000)
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#define RK3588_BUS_IOC_REG (0x8000)
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#define RK3588_VCCIO1_4_IOC_REG (0x9000)
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#define RK3588_VCCIO3_5_IOC_REG (0xA000)
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#define RK3588_VCCIO2_IOC_REG (0xB000)
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#define RK3588_VCCIO6_IOC_REG (0xC000)
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#define RK3588_EMMC_IOC_REG (0xD000)
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static const u32 rk3588_ds_regs[][2] = {
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{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
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{RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
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{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
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{RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
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{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
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{RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
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{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
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{RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
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{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
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{RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
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{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
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{RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
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{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
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{RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
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{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
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{RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
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{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
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{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
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{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
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{RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
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{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
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{RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
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{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
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{RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
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{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
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{RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
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{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
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{RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
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{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
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{RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
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{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
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{RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
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{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
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{RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
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{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
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{RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
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{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
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{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
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{RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
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{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
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{RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
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};
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static const u32 rk3588_p_regs[][2] = {
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{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
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{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
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{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
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{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
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{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
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{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
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{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
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{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
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{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
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{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
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{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
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{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
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{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
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{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
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{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
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{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
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{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
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{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
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{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
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{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
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{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
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{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
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{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
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};
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static const u32 rk3588_smt_regs[][2] = {
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{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
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{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
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{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
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{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
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{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
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{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
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{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
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{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
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{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
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{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
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{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
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{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
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{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
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{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
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{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
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{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
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{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
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{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
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{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
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{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
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{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
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{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
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{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
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};
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#define RK3588_PULL_BITS_PER_PIN 2
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#define RK3588_PULL_PINS_PER_REG 8
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static void rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *info = bank->priv;
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u8 bank_num = bank->bank_num;
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u32 pin = bank_num * 32 + pin_num;
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int i;
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for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
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if (pin >= rk3588_p_regs[i][0]) {
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*reg = rk3588_p_regs[i][1];
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break;
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}
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}
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assert(i >= 0);
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*regmap = info->regmap_base;
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*bit = pin_num % RK3588_PULL_PINS_PER_REG;
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*bit *= RK3588_PULL_BITS_PER_PIN;
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}
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#define RK3588_DRV_BITS_PER_PIN 4
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#define RK3588_DRV_PINS_PER_REG 4
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static void rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *info = bank->priv;
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u8 bank_num = bank->bank_num;
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u32 pin = bank_num * 32 + pin_num;
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int i;
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for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
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if (pin >= rk3588_ds_regs[i][0]) {
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*reg = rk3588_ds_regs[i][1];
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break;
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}
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}
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assert(i >= 0);
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*regmap = info->regmap_base;
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*bit = pin_num % RK3588_DRV_PINS_PER_REG;
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*bit *= RK3588_DRV_BITS_PER_PIN;
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}
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#define RK3588_SMT_BITS_PER_PIN 1
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#define RK3588_SMT_PINS_PER_REG 8
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static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *info = bank->priv;
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u8 bank_num = bank->bank_num;
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u32 pin = bank_num * 32 + pin_num;
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int i;
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for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
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if (pin >= rk3588_smt_regs[i][0]) {
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*reg = rk3588_smt_regs[i][1];
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break;
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}
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}
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assert(i >= 0);
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*regmap = info->regmap_base;
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*bit = pin_num % RK3588_SMT_PINS_PER_REG;
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*bit *= RK3588_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rk3588_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, translated_pull;
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u8 bit, type;
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u32 data;
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rk3588_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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translated_pull = rockchip_translate_pull_value(type, pull);
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if (translated_pull < 0) {
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debug("unsupported pull setting %d\n", pull);
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return -EINVAL;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (translated_pull << bit);
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return regmap_write(regmap, reg, data);
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}
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static int rk3588_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg;
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u32 data;
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u8 bit;
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rk3588_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3588_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (strength << bit);
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return regmap_write(regmap, reg, data);
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}
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static int rk3588_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u32 data;
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u8 bit;
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rk3588_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3588_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (enable << bit);
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return regmap_write(regmap, reg, data);
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}
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static struct rockchip_pin_bank rk3588_pin_banks[] = {
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RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
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RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
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RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
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RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
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RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
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IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
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};
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static const struct rockchip_pin_ctrl rk3588_pin_ctrl = {
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.pin_banks = rk3588_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3588_pin_banks),
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.nr_pins = 160,
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.set_mux = rk3588_set_mux,
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.set_pull = rk3588_set_pull,
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.set_drive = rk3588_set_drive,
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.set_schmitt = rk3588_set_schmitt,
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};
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static const struct udevice_id rk3588_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3588-pinctrl",
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.data = (ulong)&rk3588_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3588) = {
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.name = "rockchip_rk3588_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3588_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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