u-boot/arch/arm/mach-uniphier/clk/pll-ld11.c
Masahiro Yamada 739ba41d5a ARM: uniphier: de-couple SC macros into base address and offset
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.

Turn the SC_* macros into the offset from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-07-10 22:42:02 +09:00

45 lines
1.2 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Socionext Inc.
*/
#include <linux/delay.h>
#include <linux/io.h>
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
/* PLL type: SSC */
#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
#define SC_SPLLCTRL 0x1410 /* misc */
#define SC_MPLLCTRL 0x1430 /* DSP */
#define SC_VSPLLCTRL 0x1440 /* Video codec, VPE etc. */
#define SC_DPLLCTRL 0x1460 /* DDR memory */
/* PLL type: VPLL27 */
#define SC_VPLL27FCTRL 0x1500
#define SC_VPLL27ACTRL 0x1520
void uniphier_ld11_pll_init(void)
{
uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */
uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
mdelay(1);
uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
writel(0, sc_base + SC_CA53_GEARSET); /* Gear0: CPLL/2 */
writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD);
}