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Paul Barker bba516a772 pinctrl: rzg2l: Support Ethernet TXC output enable 
On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK
signal is selectable to support an Ethernet PHY operating in either MII
or RGMII mode. By default, the signal is configured as an input and MII
mode is supported. The ETH_MODE register can be modified to configure
this signal as an output to support RGMII mode.

As this signal is be default an input, and can optionally be switched to
an output, it maps neatly onto an `output-enable` property in the device
tree.

Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-12-08 23:06:52 +01:00
..
ddr_ctrl.h ram: cadence: add driver for Cadence EDAC 2023-05-13 04:01:30 +02:00
is43tr16256a_125k_CTL.h board: schneider: add RZN1 board support 2023-05-13 04:01:30 +02:00
jedec_ddr3_2g_x16_1333h_500_cl8.h board: schneider: add RZN1 board support 2023-05-13 04:01:30 +02:00
rzg2l-pfc.h pinctrl: rzg2l: Support Ethernet TXC output enable 2024-12-08 23:06:52 +01:00