mirror of
https://github.com/AsahiLinux/u-boot
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82e26e0d68
We like to put the SPL first so it is clear that it relates to SPL. Rename various malloc-related options which have crept in, to stick to this convention. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
162 lines
3.8 KiB
C
162 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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#ifndef __CONFIG_SOCFPGA_COMMON_H__
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#define __CONFIG_SOCFPGA_COMMON_H__
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#include <linux/stringify.h>
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/*
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* Memory configurations
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*/
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#define PHYS_SDRAM_1 0x0
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
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/* SPL memory allocation configuration, this is for FAT implementation */
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#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
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CONFIG_SPL_SYS_MALLOC_SIZE)
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#endif
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/*
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* Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
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* SRAM as bootcounter storage. Make sure to not put the stack directly
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* at this address to not overwrite the bootcounter by checking, if the
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* bootcounter address is located in the internal SRAM.
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*/
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#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \
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(CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \
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CFG_SYS_INIT_RAM_SIZE)))
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#endif
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/*
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* U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
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* phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
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* in U-Boot pre-reloc is higher than in SPL.
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*/
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#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/*
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* U-Boot general configurations
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*/
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/* Print buffer size */
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/*
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* Cache
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*/
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#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
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/*
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* L4 OSC1 Timer 0
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*/
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#ifndef CONFIG_TIMER
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#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
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#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4)
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#ifndef CFG_SYS_TIMER_RATE
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#define CFG_SYS_TIMER_RATE 25000000
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#endif
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#endif
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/*
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* L4 Watchdog
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*/
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#define CFG_DW_WDT_CLOCK_KHZ 25000
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/*
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* NAND Support
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*/
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#ifdef CONFIG_NAND_DENALI
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#define CFG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
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#define CFG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
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#endif
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/*
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* USB
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*/
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/*
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* USB Gadget (DFU, UMS)
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*/
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#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
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#define DFU_DEFAULT_POLL_TIMEOUT 300
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#endif
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/*
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* U-Boot environment
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*/
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/* Environment for SDMMC boot */
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/* Environment for QSPI boot */
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/*
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* SPL
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*
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* SRAM Memory layout for gen 5:
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*
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* 0xFFFF_0000 ...... Start of SRAM
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* 0xFFFF_xxxx ...... Top of stack (grows down)
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* 0xFFFF_yyyy ...... Global Data
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* 0xFFFF_zzzz ...... Malloc area
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* 0xFFFF_FFFF ...... End of SRAM
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*
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* SRAM Memory layout for Arria 10:
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* 0xFFE0_0000 ...... Start of SRAM (bottom)
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* 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
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* 0xFFEy_yyyy ...... Global Data
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* 0xFFEz_zzzz ...... Malloc area (grows up to top)
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* 0xFFE3_FFFF ...... End of SRAM (top)
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*/
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/* SPL QSPI boot support */
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/* SPL NAND boot support */
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/* Extra Environment */
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#ifndef CONFIG_SPL_BUILD
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#ifdef CONFIG_CMD_DHCP
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#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
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#else
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#define BOOT_TARGET_DEVICES_DHCP(func)
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#endif
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#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
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#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
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#else
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#define BOOT_TARGET_DEVICES_PXE(func)
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#endif
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#ifdef CONFIG_CMD_MMC
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#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
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#else
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#define BOOT_TARGET_DEVICES_MMC(func)
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#endif
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#define BOOT_TARGET_DEVICES(func) \
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BOOT_TARGET_DEVICES_MMC(func) \
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BOOT_TARGET_DEVICES_PXE(func) \
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BOOT_TARGET_DEVICES_DHCP(func)
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#include <config_distro_bootcmd.h>
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#ifndef CFG_EXTRA_ENV_SETTINGS
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#define CFG_EXTRA_ENV_SETTINGS \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"bootm_size=0xa000000\0" \
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"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
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"fdt_addr_r=0x02000000\0" \
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"scriptaddr=0x02100000\0" \
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"pxefile_addr_r=0x02200000\0" \
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"ramdisk_addr_r=0x02300000\0" \
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"socfpga_legacy_reset_compat=1\0" \
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BOOTENV
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#endif
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#endif
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#endif /* __CONFIG_SOCFPGA_COMMON_H__ */
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