mirror of
https://github.com/AsahiLinux/u-boot
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0f02269b76
Skip setting parent with dummy fixed-clock. Upstream linux might declare
an additional clock for the mtk timer and that additional clock might
also be a fixed-clock defined in DT. Setting parent of a dummy fixed-clock
resulta in error hence mtk timer fails to probe.
Skip setting parent to permit correct probe of the mtk timer.
Fixes: d3c3606c5c ("timer: MediaTek: add timer driver for MediaTek SoCs")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek timer driver
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*
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* Copyright (C) 2018 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#define MTK_GPT4_OFFSET_V1 0x40
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#define MTK_GPT4_OFFSET_V2 0x80
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#define MTK_GPT_CON 0x0
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#define MTK_GPT_V1_CLK 0x4
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#define MTK_GPT_CNT 0x8
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#define GPT_ENABLE BIT(0)
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#define GPT_CLEAR BIT(1)
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#define GPT_V1_FREERUN GENMASK(5, 4)
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#define GPT_V2_FREERUN GENMASK(6, 5)
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enum mtk_gpt_ver {
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MTK_GPT_V1,
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MTK_GPT_V2
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};
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struct mtk_timer_priv {
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void __iomem *base;
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unsigned int gpt4_offset;
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};
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static u64 mtk_timer_get_count(struct udevice *dev)
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{
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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u32 val = readl(priv->base + priv->gpt4_offset + MTK_GPT_CNT);
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return timer_conv_64(val);
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}
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static int mtk_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mtk_timer_priv *priv = dev_get_priv(dev);
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struct clk clk, parent;
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int ret, gpt_ver;
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priv->base = dev_read_addr_ptr(dev);
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gpt_ver = dev_get_driver_data(dev);
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if (!priv->base)
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return -ENOENT;
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if (gpt_ver == MTK_GPT_V2) {
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priv->gpt4_offset = MTK_GPT4_OFFSET_V2;
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writel(GPT_V2_FREERUN | GPT_CLEAR | GPT_ENABLE,
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priv->base + priv->gpt4_offset + MTK_GPT_CON);
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} else {
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priv->gpt4_offset = MTK_GPT4_OFFSET_V1;
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writel(GPT_V1_FREERUN | GPT_CLEAR | GPT_ENABLE,
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priv->base + priv->gpt4_offset + MTK_GPT_CON);
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writel(0, priv->base + priv->gpt4_offset + MTK_GPT_V1_CLK);
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}
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_get_by_index(dev, 1, &parent);
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/* Skip setting the parent with dummy fixed-clock */
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if (!ret && parent.dev->driver != DM_DRIVER_GET(fixed_clock)) {
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ret = clk_set_parent(&clk, &parent);
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if (ret)
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return ret;
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}
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uc_priv->clock_rate = clk_get_rate(&clk);
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if (!uc_priv->clock_rate)
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return -EINVAL;
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return 0;
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}
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static const struct timer_ops mtk_timer_ops = {
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.get_count = mtk_timer_get_count,
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};
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static const struct udevice_id mtk_timer_ids[] = {
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{ .compatible = "mediatek,timer", .data = MTK_GPT_V1 },
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{ .compatible = "mediatek,mt6577-timer", .data = MTK_GPT_V1 },
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{ .compatible = "mediatek,mt7981-timer", .data = MTK_GPT_V2 },
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{ .compatible = "mediatek,mt7986-timer", .data = MTK_GPT_V2 },
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{ }
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};
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U_BOOT_DRIVER(mtk_timer) = {
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.name = "mtk_timer",
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.id = UCLASS_TIMER,
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.of_match = mtk_timer_ids,
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.priv_auto = sizeof(struct mtk_timer_priv),
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.probe = mtk_timer_probe,
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.ops = &mtk_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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