mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
118 lines
2.6 KiB
C
118 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2020 Linumiz
|
|
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
|
|
*/
|
|
|
|
#include <init.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <asm/arch/mx6-pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/mach-imx/mxc_i2c.h>
|
|
#include <fsl_esdhc_imx.h>
|
|
#include <linux/bitops.h>
|
|
#include <miiphy.h>
|
|
#include <netdev.h>
|
|
#include <usb.h>
|
|
#include <usb/ehci-ci.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
|
|
PAD_CTL_HYS)
|
|
|
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
|
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const uart5_pads[] = {
|
|
MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_iomux_uart(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
|
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
|
|
}
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
|
|
static int setup_fec(void)
|
|
{
|
|
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
int ret;
|
|
|
|
/*
|
|
* Use 50M anatop loopback REF_CLK1 for ENET1,
|
|
* clear gpr1[13], set gpr1[17].
|
|
*/
|
|
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
|
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
|
|
|
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
enable_enet_clk(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
/*
|
|
* Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
|
|
* 50 MHz RMII clock mode.
|
|
*/
|
|
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
|
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_FEC_MXC */
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* Address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
setup_fec();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
u32 cpurev = get_cpu_rev();
|
|
|
|
printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
|
|
get_imx_type((cpurev & 0xFF000) >> 12));
|
|
|
|
return 0;
|
|
}
|