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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Calxeda Highbank/Midway "system registers" bus driver
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*
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* There is a "clocks" subnode inside the top node, which groups all clocks,
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* both programmable PLLs as well as fixed clocks.
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* Simple allow the DT enumeration to look inside this node, so that we can
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* read the fixed clock frequencies using the DM clock framework.
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*
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* Copyright (C) 2019 Arm Ltd.
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*/
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#include <dm.h>
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#include <dm/lists.h>
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static int hb_sregs_scan_fdt_dev(struct udevice *dev)
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{
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ofnode clock_node, node;
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/* Search for subnode called "clocks". */
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ofnode_for_each_subnode(clock_node, dev_ofnode(dev)) {
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if (!ofnode_name_eq(clock_node, "clocks"))
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continue;
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/* Enumerate all nodes inside this "clocks" subnode. */
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ofnode_for_each_subnode(node, clock_node)
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lists_bind_fdt(dev, node, NULL, NULL, false);
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return 0;
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}
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return -ENOENT;
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}
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static const struct udevice_id highbank_sreg_ids[] = {
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{ .compatible = "calxeda,hb-sregs" },
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{}
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};
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U_BOOT_DRIVER(hb_sregs) = {
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.name = "hb-sregs",
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.id = UCLASS_SIMPLE_BUS,
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.bind = hb_sregs_scan_fdt_dev,
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.of_match = highbank_sreg_ids,
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};
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