// SPDX-License-Identifier: GPL-2.0+ OR MIT

#include "imx7s-u-boot.dtsi"

/ {
	wdt-reboot {
		compatible = "wdt-reboot";
		wdt = <&wdog1>;
		bootph-pre-ram;
	};
};

&fec2 {
	status = "disable";
};

&usbotg1 {
	dr_mode = "peripheral";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
};

&pinctrl_usdhc1 {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
		>;
};

&iomuxc {
	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
		fsl,pins = <
			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
		>;
	};
};

&wdog1 {
	bootph-pre-ram;
};