// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2022 MediaTek Inc. * Author: Sam Shih <sam.shih@mediatek.com> */ /dts-v1/; #include "mt7986.dtsi" #include <dt-bindings/gpio/gpio.h> / { #address-cells = <1>; #size-cells = <1>; model = "mt7986-rfb"; compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; chosen { stdout-path = &uart0; tick-timer = &timer0; }; memory@40000000 { device_type = "memory"; reg = <0x40000000 0x10000000>; }; reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &uart0 { status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; status = "disabled"; }; ð { status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; full-duplex; }; }; &pinctrl { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; drive-strength = <MTK_DRIVE_8mA>; bias-pull-up = <MTK_PUPD_SET_R1R0_11>; }; conf-pd { pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; drive-strength = <MTK_DRIVE_8mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_11>; }; }; snfi_pins: snfi-pins-func-1 { mux { function = "flash"; groups = "snfi"; }; clk { pins = "SPI0_CLK"; drive-strength = <MTK_DRIVE_8mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_00>; }; conf-pu { pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; drive-strength = <MTK_DRIVE_6mA>; bias-pull-up = <MTK_PUPD_SET_R1R0_00>; }; conf-pd { pins = "SPI0_MOSI", "SPI0_MISO"; drive-strength = <MTK_DRIVE_6mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_00>; }; }; spic_pins: spi1-pins-func-1 { mux { function = "spi"; groups = "spi1_2"; }; }; uart1_pins: spi1-pins-func-3 { mux { function = "uart"; groups = "uart1_2"; }; }; pwm_pins: pwm0-pins-func-1 { mux { function = "pwm"; groups = "pwm0"; }; }; mmc0_pins_default: mmc0default { mux { function = "flash"; groups = "emmc_45"; input-schmitt-enable; }; conf-cmd-dat { pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", "SPI0_CS", "SPI0_HOLD", "SPI0_WP", "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; input-enable; drive-strength = <MTK_DRIVE_4mA>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; conf-clk { pins = "SPI1_CS"; drive-strength = <MTK_DRIVE_6mA>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; conf-rst { pins = "PWM1"; drive-strength = <MTK_DRIVE_4mA>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; }; &snand { pinctrl-names = "default"; pinctrl-0 = <&snfi_pins>; status = "okay"; quad-spi; }; &spi0 { #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; must_tx; enhance_timing; dma_ext; ipm_design; support_quad; tick_dly = <2>; sample_sel = <0>; spi_nor@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; }; spi_nand@1 { compatible = "spi-nand"; reg = <1>; spi-max-frequency = <52000000>; }; }; &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; status = "okay"; }; &watchdog { status = "disabled"; }; &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_default>; bus-width = <8>; max-frequency = <52000000>; cap-mmc-highspeed; cap-mmc-hw-reset; vmmc-supply = <®_3p3v>; non-removable; status = "okay"; };