// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015 - 2020, Xilinx, Inc. * * Michal Simek <michal.simek@amd.com> * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ /dts-v1/; #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; &dcc { status = "okay"; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &uart0 { status = "okay"; };