// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2019 A. Karas, SomLabs * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. */ #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> #include <common.h> #include <env.h> #include <fsl_esdhc_imx.h> #include <i2c.h> #include <miiphy.h> #include <linux/sizes.h> #include <mmc.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) int dram_init(void) { gd->ram_size = imx_ddr_size(); return 0; } static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #ifdef CONFIG_FEC_MXC static int setup_fec(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; /* * Use 50M anatop loopback REF_CLK1 for ENET1, * clear gpr1[13], set gpr1[17]. */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; enable_enet_clk(1); return 0; } int board_phy_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); if (phydev->drv->config) phydev->drv->config(phydev); return 0; } #endif int board_mmc_get_env_dev(int devno) { return devno; } int mmc_map_to_kernel_blk(int devno) { return devno; } int board_early_init_f(void) { setup_iomux_uart(); return 0; } int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif #ifdef CONFIG_FEC_MXC setup_fec(); #endif return 0; } #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, {NULL, 0}, }; #endif int board_late_init(void) { #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif if (is_cpu_type(MXC_CPU_MX6ULL)) env_set("board", "visionsom-6ull"); else env_set("board", "visionsom-6ul"); return 0; } int checkboard(void) { printf("Board: SoMLabs VisionSOM-6UL%s\n", is_cpu_type(MXC_CPU_MX6ULL) ? "L" : ""); return 0; }