/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd */ #ifndef __CONFIG_RK3308_COMMON_H #define __CONFIG_RK3308_COMMON_H #include "rockchip-common.h" #define CONFIG_IRAM_BASE 0xfff80000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x02800000\0" \ "kernel_addr_r=0x00680000\0" \ "ramdisk_addr_r=0x04000000\0" #include #define CONFIG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ BOOTENV #endif