// SPDX-License-Identifier: GPL-2.0+ OR MIT /* * Copyright (C) 2022 Kontron Electronics GmbH */ #include #include "imx8mm.dtsi" / { model = "Kontron OSM-S i.MX8MM (N802X SOM)"; compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm"; aliases { rtc0 = &rv3028; rtc1 = &snvs_rtc; }; memory@40000000 { device_type = "memory"; /* * There are multiple SoM flavors with different DDR sizes. * The smallest is 1GB. For larger sizes the bootloader will * update the reg property. */ reg = <0x0 0x40000000 0 0x80000000>; }; chosen { stdout-path = &uart3; }; }; &A53_0 { cpu-supply = <®_vdd_arm>; }; &A53_1 { cpu-supply = <®_vdd_arm>; }; &A53_2 { cpu-supply = <®_vdd_arm>; }; &A53_3 { cpu-supply = <®_vdd_arm>; }; &ddrc { operating-points-v2 = <&ddrc_opp_table>; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; opp-100M { opp-hz = /bits/ 64 <100000000>; }; opp-750M { opp-hz = /bits/ 64 <750000000>; }; }; }; &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency = <80000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "u-boot"; reg = <0x0 0x1e0000>; }; partition@1e0000 { label = "env"; reg = <0x1e0000 0x10000>; }; partition@1f0000 { label = "env_redundant"; reg = <0x1f0000 0x10000>; }; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; pca9450: pmic@25 { compatible = "nxp,pca9450a"; reg = <0x25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; regulators { reg_vdd_soc: BUCK1 { regulator-name = "+0V8_VDD_SOC (BUCK1)"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <850000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <850000>; nxp,dvs-standby-voltage = <800000>; }; reg_vdd_arm: BUCK2 { regulator-name = "+0V9_VDD_ARM (BUCK2)"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; }; reg_vdd_dram: BUCK3 { regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; }; reg_vdd_3v3: BUCK4 { regulator-name = "+3V3 (BUCK4)"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; reg_vdd_1v8: BUCK5 { regulator-name = "+1V8 (BUCK5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; reg_nvcc_dram: BUCK6 { regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; reg_nvcc_snvs: LDO1 { regulator-name = "+1V8_NVCC_SNVS (LDO1)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; reg_vdd_snvs: LDO2 { regulator-name = "+0V8_VDD_SNVS (LDO2)"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; }; reg_vdda: LDO3 { regulator-name = "+1V8_VDDA (LDO3)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; reg_vdd_phy: LDO4 { regulator-name = "+0V9_VDD_PHY (LDO4)"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; }; reg_nvcc_sd: LDO5 { regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; trickle-diode-disable; }; }; &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; vmmc-supply = <®_vdd_3v3>; vqmmc-supply = <®_vdd_1v8>; bus-width = <8>; non-removable; status = "okay"; }; &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; fsl,ext-reset-output; status = "okay"; }; &iomuxc { pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 >; }; pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 >; }; };